PC87338 Datasheet, PDF (8/221 Pages) National Semiconductor (TI) – ACPI 1.0 and PC98/99 Compliant SuperI/O

4.3.10 EPP Data Port 3, Offset 7 ................................................................................................... 131
4.3.11 EPP Mode Transfer Operations .......................................................................................... 131
4.4 EXTENDED CAPABILITIES PARALLEL PORT (ECP) MODES .................................................... 133
4.4.1 Accessing the ECP Registers ............................................................................................... 134
4.4.2 Software Operation in ECP Modes ....................................................................................... 134
4.4.3 Hardware Operation in ECP Modes ...................................................................................... 134
4.4.4 ECP Modes Parallel Port Register Bitmaps .......................................................................... 135
4.4.5 ECP Data Register (DATAR), Bits 7-5 of ECR = 000 or 001, Offset 000h ............................ 136
4.4.6 ECP Address FIFO (AFIFO) Register, Bits 7-5 of ECR = 011, Offset 000h .......................... 137
4.4.7 ECP Status Register (DSR), Offset 001h .............................................................................. 137
4.4.8 ECP Control Register (DCR), Offset 002h ............................................................................ 137
4.4.9 Parallel Port Data FIFO (CFIFO) Register, Bits 7-5 of ECR = 010, Offset 400h ................... 138
4.4.10 ECP Data FIFO (DFIFO) Register, Bits 7-5 of ECR = 011, Offset 400h ............................. 138
4.4.11 Test FIFO (TFIFO) Register, Bits 7-5 of ECR = 110, Offset 400h ...................................... 139
4.4.12 Configuration Register A (CNFGA), Bits 7-5 of ECR = 111, Offset 400h ............................ 139
4.4.13 Configuration Register B (CNFGB), Bits 7-5 of ECR = 111, Offset 401h ............................ 139
4.4.14 Extended Control Register (ECR), Offset 402h ................................................................... 140
4.5 ECP MODE DESCRIPTIONS ......................................................................................................... 142
4.5.1 Software Controlled Data Transfer (Modes 000 and 001) ..................................................... 142
4.5.2 Automatic Data Transfer (Modes 010 and 011) .................................................................... 142
4.5.3 FIFO Test Access (Mode 110) .............................................................................................. 143
4.5.4 Configuration Registers Access (Mode 111) ......................................................................... 143
4.5.5 Interrupt Generation .............................................................................................................. 143
4.6 THE PARALLEL PORT MULTIPLEXER (PPM) ............................................................................. 144
4.7 PARALLEL PORT PIN/SIGNAL LIST ............................................................................................. 144
5.0 Serial Communications Controllers (SCC1 and SCC2)
5.1 FEATURES ..................................................................................................................................... 146
5.2 FUNCTIONAL MODES OVERVIEW .............................................................................................. 146
5.3 UART MODE .................................................................................................................................. 146
5.4 SHARP-IR MODE ........................................................................................................................... 147
5.5 IRDA 1.0 SIR MODE ...................................................................................................................... 147
5.6 IRDA 1.1 MIR AND FIR MODES .................................................................................................... 147
5.6.1 High Speed Infrared Transmit Operation .............................................................................. 148
5.6.2 High Speed Infrared Receive Operation ............................................................................... 149
5.7 CONSUMER ELECTRONIC IR (CEIR) MODE .............................................................................. 149
5.7.1 CEIR Transmit Operation ...................................................................................................... 149
5.7.2 CEIR Receive Operation ....................................................................................................... 150
5.8 FIFO TIME-OUTS ........................................................................................................................... 150
5.9 TRANSMIT DEFERRAL ................................................................................................................. 151
5.10 AUTOMATIC FALLBACK TO 16550 COMPATIBILITY MODE .................................................... 151
5.11 PIPELINING .................................................................................................................................. 152
5.12 OPTICAL TRANSCEIVER INTERFACE ...................................................................................... 152
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