PC87338 Datasheet, PDF (52/221 Pages) National Semiconductor (TI) – ACPI 1.0 and PC98/99 Compliant SuperI/O

Bit 3 - MIDI/Reserved
In the PC87338 version this is the MIDI baud rate
configuration bit which function as follow:
0 - The SCC1 baud rate generator is fed by the
master clock of the Chip, divided by 13.
1 - The SCC1 baud rate generator is fed by the
master clock of the Chip divided by 12. This bit
should be set to support a MIDI port.
This bit is reserved in the PC97338 version.
Bit 4 - Reserved
This bit is reserved.
Bit 5 - PD Status
This bit holds the FDC power-down state, as de-
fined for the PD pin, even when pin 45 (or 43 for
VJG package) is not configured as PD. This bit is
read only.
Bit 6 - IDLE Status
This bit holds the FDC idle state, as defined for the
IDLE pin, even when pin 43 (or pin 41 in the VJG
package) is not configured as IDLE, and when
IDLE is masked by bit 7 of TUP. This bit is read
only.
Bit 7 - IDLE Pin Mask
This bit masks the IDLE output pin (but not the
IDLE status bit). This bit is ignored when pin 43 is
not configured as IDLE.
0 - The IDLE output pin is unmasked The IDLE
pin drives the value of the FDC idle state.
1 - The IDLE output pin is masked. The IDLE pin
is driven low.
2.3.9 SuperI/O Chip Identification
Register (SID), Index 08h
The SID register is accessed, like the other configura-
tion registers, through the INDEX register.
This read-only register identifies the chip. Bits 2-0
contain the revision code. SID holds the value B0h.
76543210
1 0 1 1 0 X X X Reset
1 0 1 1 0 X X X Required
SuperI/O Chip
Identification
Register (SID)
Index 08h
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 10. SID Register Bitmap
2.3.10 Advanced SuperI/O Chip
Configuration Register
(ASC), Index 09h
During reset, bits 2-0 and bits 5,4 are initialized to 0,
and bits 7,6 are initialized to 1 (1100X000).
Advanced SuperI/O Chip
7 6 5 4 3 2 1 0 Configuration Register
1 1 0 0 X 0 0 0 Reset
Required
(ASC)
Index 09h
Select IRQ5 or ADRATE0
Reserved
Enhanced TDR Support
PNF Status
Select DENSEL or ADRATE1
ECP CNFGA Bit
DENSEL Polarity Select
System Operation Mode
FIGURE 11. ASC Register Bitmap
Bit 0 - Select IRQ5 or ADRATE0
In Plug and Play mode, this bit does not affect the
interrupt mapping of the parallel port (even when
ADRATE0 is selected).
In Legacy mode, selection of parallel port interrupt
pin (IRQ5 or IRQ7) via bits 1 and 0 of FAR, and via
bit 3 of PTR, is ignored and IRQ7 is used as paral-
lel port interrupt.
0 - Pin 98 (PQFP) or pin 96 (TQFP) is IRQ5.
IRQ5 is controlled by bits 6 and 5 of PCR.
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