PC87338 Datasheet, PDF (15/221 Pages) National Semiconductor (TI) – ACPI 1.0 and PC98/99 Compliant SuperI/O

List of Tables
TABLE 1 Signal/Pin Description Table ............................................................................................................ 22
TABLE 2 Multi-Function Pins (Excluding Strap Pins) ...................................................................................... 34
TABLE 3 IRQ12, A15-11 / SCC2 / Infrared Pin Allocation ............................................................................... 35
TABLE 4 SCC2 Mode Configurations 1 ........................................................................................................... 35
TABLE 5 SCC2 Mode Configurations 2 .......................................................................................................... 35
TABLE 6 Default Configurations Controlled by Hardware .............................................................................. 36
TABLE 7 Configuration Registers ................................................................................................................... 36
TABLE 8 INDEX and DATA Register Address Options and Configuration Register Accessibility .................. 38
TABLE 9 Primary and Secondary Drive Address Selection ............................................................................ 46
TABLE 10 Encoded Drive and Motor Pin Information (Bit 4 of FER = 1) ......................................................... 46
TABLE 11 Parallel Port Addresses .................................................................................................................. 47
TABLE 12 COM Port Selection for SCC1 ........................................................................................................ 47
TABLE 13 COM Port Selection for SCC2 ........................................................................................................ 47
TABLE 14 Address Selection for COM3 and COM4 ...................................................................................... 47
TABLE 15 Parallel Port Mode .......................................................................................................................... 49
TABLE 16 Bit Settings to Enable MRT1, IDLE or IRSL2 ................................................................................ 51
TABLE 17 Bit Settings to Enable DR1 or PD .................................................................................................. 51
TABLE 18 ECP DMA Option Selection ........................................................................................................... 56
TABLE 19 Parallel Port Plug and Play DMA Settings ..................................................................................... 56
TABLE 20 Parallel Port Plug and Play Interrupt Assignment .......................................................................... 57
TABLE 21 Parallel Port Plug and Play Interrupt Mapping ............................................................................. 57
TABLE 22 TDR Bit 5 Values ............................................................................................................................ 58
TABLE 23 FDC Plug and Play Interrupt Mapping ........................................................................................... 59
TABLE 24 FDC Plug and Play DMA Settings .................................................................................................. 60
TABLE 25 SBAL Reset Values ....................................................................................................................... 63
TABLE 26 SBAH Reset Values ...................................................................................................................... 63
TABLE 27 SIRQI1 Plug and Play Interrupt Mapping ....................................................................................... 64
TABLE 28 SIRQ1 Interrupt Settings
64
TABLE 29 SIRQI2 Plug and Play Interrupt Mapping .................................................................................... 65
TABLE 30 Selecting MSEN1, DRATE1, CS0 or SIRQI2 ................................................................................. 65
TABLE 31 SIRQI3 Plug and Play Interrupt Mapping ...................................................................................... 66
TABLE 32 Selecting DRV2, DR23, PNF or SIRQI3 .................................................................................. 66
TABLE 33 SCC2 Receiver Channel Selection ............................................................................................... 67
TABLE 34 SCC2 Transmission Channel Selection ......................................................................................... 67
TABLE 35 The FDC Registers and Their Addresses ...................................................................................... 74
TABLE 36 Drive and Motor Pin Encoding When FER 4 = 1 ........................................................................... 77
TABLE 37 Drive Enable Hexadecimal Values ................................................................................................. 77
TABLE 38 TDR Bit Utilization and Reset Values in Different Drive Modes ..................................................... 79
TABLE 39 Media Type Bit Settings ................................................................................................................ 80
TABLE 40 Data Transfer Rate Encoding ......................................................................................................... 82
TABLE 41 Write Precompensation Delays ...................................................................................................... 82
TABLE 42 Default Precompensation Delays ................................................................................................... 82
TABLE 43 FDC Command Set Summary ........................................................................................................ 92
TABLE 44 Bytes per Sector Codes ................................................................................................................. 97
TABLE 45 Typical Values for PC Compatible Diskette Media ......................................................................... 97
TABLE 46 Typical Gap Values ........................................................................................................................ 98
TABLE 47 Multipliers and Head Settle Time Ranges for Different Data Transfer Rates .............................. 102
TABLE 48 DENSEL Encoding ...................................................................................................................... 102
TABLE 49 Effect of Drive Mode and Data Rate on FORMAT TRACK and WRITE DATA Commands ......... 104
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