PC87338 Datasheet, PDF (42/221 Pages) National Semiconductor (TI) – ACPI 1.0 and PC98/99 Compliant SuperI/O

Advanced SuperI/O Chip
7 6 5 4 3 2 1 0 Configuration Register
1 1 0 0 x 0 0 0 Reset
Required
(ASC)
Index 09h
Select IRQ5 or ADRATE0
Reserved
Enhanced TDR Support
PNF Status
Select DENSEL or ADRATE1
ECP CNFGA Bit
DENSEL Polarity Select
System Operation Mode
Chip Select 0
7 6 5 4 3 2 1 0 Low Address Register
Reset
Required
(CS0LA)
Index 0Ah
A0
A1
A2
A3
A4
A5
A6
A7
Chip Select 0
7 6 5 4 3 2 1 0 Configuration Register
0 0 0 0 0 0 0 0 Reset
Required
(CS0CF)
Index 0Bh
Reserved
Reserved
Reserved
Number of Decoded Address Bits
CS0 Assert Enable (Write)
CS0 Assert Enable (Read)
Reserved
Reserved
Chip Select 1
7 6 5 4 3 2 1 0 ^{Low Address Register}
Reset
Required
(CS1LA)
Index 0Ch
A0
A1
A2
A3
A4
A5
A6
A7
Chip Select 1
7 6 5 4 3 2 1 0 Configuration Register
0 0 0 0 0 0 0 0 Reset
Required
(CS1CF)
Index 0Dh
Reserved
Reserved
Reserved
Number of Decoded Address Bits
CS1 Assert Enable (Write)
CS1 Assert Enable (Read)
Reserved
Reserved
Chip Select 0
7 6 5 4 3 2 1 0 High Address Register
Reset
Required
(CS0HA)
Index 10h
Address Length
CFG0 = 1 CFG0 = 0
11 Bits
16 bits
A8
A8
A9
A9
A10
A10
Reserved
A11
Reserved
A12
Reserved
A13
Reserved
A14
Reserved
A15
Chip Select 1
7 6 5 4 3 2 1 0 High Address Register
Reset
Required
(CS1HA)
Index 11h
Address Length
CFG0 = 1 CFG0 = 0
11 Bits
16 bits
A8
A8
A9
A9
A10
A10
Reserved
A11
Reserved
A12
Reserved
A13
Reserved
A14
Reserved
A15
76543210
SuperI/O Chip
Configuration
x x x x 0 x x x Reset _{Register 0 (SCF0)}
Required
Index 12h
Reserved
Reserved
Reserved
UART TRI-STATE Control
Reserved
Reserved
Reserved
Reserved
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