PC87338 Datasheet, PDF (166/221 Pages) National Semiconductor (TI) – ACPI 1.0 and PC98/99 Compliant SuperI/O

5.16.2 EXCR1 – Extended Control
Register 1
Used to control the extended mode of operation.
Upon reset all bits are set to 0.
76543210
0 0 0 0 0 0 0 0 Reset
1
Required
EXT_SL
DMANF
DMATH
DMASWP
LOOP
ETDLBK
Reserved
BTEST
FIGURE 88. Extended Control Register 1
B0 EXTSL – Extended Mode Select.
When set to 1, extended mode is selected.
B1 DMANF – DMA Fairness Control.
This bit controls the maximum duration of DMA
burst transfers.
0 → DMA requests are forced inactive after ap-
proximately 10.5 µs of continuous transmitter
and/or receiver DMA operation.
1 → A TXDMA request is deactivated when the
TX_FIFO is full.
An RX_DMA request is deactivated when the
RX_FIFO is empty.
B2 DMATH – DMA Threshold Levels Select.
This bit selects the TX_FIFO and RX_FIFO
threshold levels used by the DMA request logic to
support demand transfer mode.
A TX_DMA request is generated when the
TX_FIFO level is below the threshold.
An RXDMA request is generated when the
RX_FIFO level reaches the threshold or when an
RX_FIFO time-out occurs.
Bit
Value
RX_FIFO
DMA Thrsh.
TX_FIFO
DMA
Thresh.
(16-Levels)
TX_FIFO
DMA
Thresh.
(32-Levels)
0
4
13
29
1
10
7
23
B3 DMASWP – DMA Swap.
This bit selects the routing of the DMA control
signals between the internal DMA logic and the
configuration module. When this bit is 0, the
transmitter and receiver DMA control signals are
not swapped. When it is 1, they are swapped. A
block diagram illustrating the control signals
routing is given in Table 88.
The swap feature is particularly useful when
only one 8237 DMA channel is used to serve
both transmitter and receiver. In this case only
one external DRQ/DACK signal pair will be in-
terconnected to the swap logic by the configura-
tion module. Routing the external DMA channel
to either the transmitter or the receiver DMA log-
ic is then simply controlled by the DMASWP bit.
This way, the infrared module drivers do not
need to know the details of the configuration
module.
B4 LOOP – Loopback Enable.
When set to 1, loopback mode is selected. This
bit accesses the same internal register as bit 4
in the MCR register, when the module is in non-
extended mode.
Loopback mode behaves similarly in both non-
extended and extended modes.
When extended mode is selected, the DTR bit in
the MCR register internally drives both DSR and
RI, and the RTS bit drives CTS and DCD.
During loopback the following occur:
1. The transmitter and receiver interrupts are
fully operational. The modem status inter-
rupts are also fully operational, but the inter-
rupts' sources are now the lower bits of the
MCR register. Modem interrupts in infrared
modes are disabled unless the IRMSSL bit in
the IRCR2 register is 0. Individual interrupts
are still controlled by the IER register bits.
2. The DMA control signals are fully operation-
al.
3. UART and infrared receiver serial input pins
are disconnected. The internal receiver seri-
al inputs are connected to the corresponding
internal transmitter serial outputs.
4. The UART transmitter serial output pin is
forced high and the infrared transmitter serial
output pin is forced low, unless the ETDLBK
bit is set to 1. In which case they will function
normally.
5. The modem status input pins (DSR, CTS, RI
and DCD) are disconnected. The internal
modem status signals, are driven by the low-
er bits of the MCR register.
B5 ETDLBK – Enable Transmitter Output During
Loopback.
When set to 1, the transmitter serial output is en-
abled and functions normally when loopback is
selected.
B6 Reserved.
Write 1.
B7 BTEST – Baud Generator Test.
When set to 1, the output of the baud generator
is routed to the DTR pin.
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