DS90C3201_06 Datasheet, PDF (8/20 Pages) National Semiconductor (TI) – 3.3V 8 MHz to 135MHz Dual FPD-LIink Transmitter

AC Timing Diagrams (Continued)
FIGURE 6. Input Clock Transition Time
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FIGURE 7. Input Setup/Hold Time, High/Low Time, and Clock In to Clock Out Latency
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
Note 8: The incremental test pattern tests device power consumption for a “typical” LCD display pattern.
Note 9: Figures 2, 4, 7 show a falling edge data strobe (TCLK IN).
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FIGURE 8. Phase Lock Loop Set Time
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