DS90C3201_06 Datasheet, PDF (5/20 Pages) National Semiconductor (TI) – 3.3V 8 MHz to 135MHz Dual FPD-LIink Transmitter

Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
LLHT
LVDS Low-to-High Transition Time (Figure 5)
LHLT
LVDS High-to-Low Transition Time (Figure 5)
TPPos1
Transmitter Output Pulse Position for bit 1 (1st bit) (Figure 13)
−0.2
TPPos0
Transmitter Output Pulse Position for bit 0 (2nd bit) (Figure 13) 1 UI − 0.2
TPPos6
Transmitter Output Pulse Position for bit 6 (3rd bit) (Figure 13) 2 UI − 0.2
TPPos5
Transmitter Output Pulse Position for bit 5 (4th bit) (Figure 13) 3 UI − 0.2
TPPos4
Transmitter Output Pulse Position for bit 4 (5th bit) (Figure 13) 4 UI − 0.2
TPPos3
Transmitter Output Pulse Position for bit 3 (6th bit) (Figure 13) 5 UI − 0.2
TPPos2
Transmitter Output Pulse Position for bit 2 (7th bit) (Figure 13) 6 UI − 0.2
TSTC
Required TxIN Setup to TCLK IN (Figure 7)
1.5
Register addr 26d/19h bit [2:0] = 000b (Default)
THTC
Required TxIN Hold to TCLK IN (Figure 7)
1.5
Register addr 26d/19h bit [2:0] = 000b (Default)
TSTC/THTC Register addr 26d/19h bit [2:0] = 001b (Figure 12)
Programmable Decrease TSTC ^~400ps from Default;
adjustment
Increase THTC ^~400ps from Default
Register addr 26d/19h bit [2:0] = 010b,
Decrease TSTC ^~800ps from default;
Increase THTC ^~800ps from Default
Register addr 26d/19h bit [2:0] = 011b,
Decrease TSTC ^~1200ps from Default;
Increase THTC ^~1200ps from Default
Register addr 26d/19h bit [2:0] = 111b,
Increase TSTC ^~800ps from Default;
Decrease THTC ^~800ps from Default
Register addr 26d/19h bit [2:0] = 110b,
Increase TSTC ^~600ps from Default;
Decrease THTC ^~600ps from Default
Register addr 26d/19h bit [2:0] = 101b,
Increase TSTC ^~400ps from Default;
Decrease THTC ^~400ps from Default
Register addr 26d/19h bit [2:0] = 100b,
Increase TSTC ^~200ps from Default;
Decrease THTC ^~200ps from Default
TCCD
Transmitter TCLKIN (LVTTL) to CLKOUT (LVDS) Latency
(Figure 7)
f = 8 MHz
10
f = 25 MHz
20
f = 40 MHz
25
f = 65 MHz
40
f = 85 MHz
60
f = 135 MHz
180
TPPLS
Transmitter Phase Lock Loop Set (Figure 8)
TPDD
Transmitter Powerdown Delay (Figure 9)
Typ
0.6
0.6
0
1
2
3
4
5
6
0.69
0.70
0.5/
1.0
0/
1.5
-0.5/
2.0
1.5/
0
1.4/
0
1.1/
0.3
0.9/
0.5
Max
1.5
1.5
+0.2
1 UI + 0.2
2 UI + 0.2
3 UI + 0.2
4 UI + 0.2
5 UI + 0.2
6 UI + 0.2
Units
ns
ns
UI
UI
UI
UI
UI
UI
UI
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
30
ns
40
ns
50
ns
70
ns
200
ns
10
ms
100
ns
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage and temperature ranges. This
parameter is functional tested only on Automatic Test Equipment (ATE).
Note 6: A Unit Interval (UI) is defined as 1/7th of an ideal clock period (TCIP/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns (Figure 11)
5
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