DS90C3201_06 Datasheet, PDF (19/20 Pages) National Semiconductor (TI) – 3.3V 8 MHz to 135MHz Dual FPD-LIink Transmitter

DS90C3201 Two-Wire Serial Interface Register Table (Continued)
Address
31d/1fh
R/W
R/W
RESET
PWDN
Bit #
[7:6]
[5]
[0:4]
Description
11: LVDS O/Ps available as long as "NO CLK" is at
HIGH regardless PLL lock or not
10: LVDS O/Ps available after 1K of TCLK cycles
detected & PLL generated strobes are within 0.5UI
respect to REFCLK
01: LVDS O/Ps available after 2K of TCLK cycles
detected
00: Default ; LVDS O/Ps available after 1K of TCLK
cycles detected
0: Default; to select the size of wait counter between 1K
or 2K, Default is 1K
Reserved
Default Value
0000_0000
19
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