DS90C3201_06 Datasheet, PDF (13/20 Pages) National Semiconductor (TI) – 3.3V 8 MHz to 135MHz Dual FPD-LIink Transmitter

DS90C3201 Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Pin Name
TXEC3
TXEC4
TXEC5
TXEC6
TXEB0
TXEB1
TXEB2
TXEB3
TXEB4
TXEB5
TXEB6
VDDE1
VSSE1
TXEA0
TXEA1
TXEA2
TXEA3
TXEA4
TXEA5
TXEA6
VDDP1
VSSP1
VSSP0
VDDP0
VDDT0
VSST0
TCLKIN
VDDI
VSSI
PWDNB
I/O
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
VDD
GND
I/P
I/P
I/P
I/P
I/P
I/P
I/P
VDD
GND
GND
VDD
VDD
GND
I/P
VDD
GND
I/P
Pin Type
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
DIGITAL
DIGITAL
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
LVTTL I/P (pulldown)
PLL
PLL
PLL
PLL
TX LOGIC
TX LOGIC
LVTTL I/P (pulldown)
DIGITAL
DIGITAL
LVTTL I/P (pulldown)
31
S2CLK
I/P
DIGITAL
32
S2DAT
I/OP DIGITAL
33
RFB
VDD LVTTL I/P (pulldown)
34
MODE0
I/P
LVTTL I/P (pulldown)
35
VDDL
VDD ANALOG
36
VSSL
GND ANALOG
37
TXEE+
O/P LVDS O/P
38
TXEE -
O/P LVDS O/P
39
TXED+
O/P LVDS O/P
40
TXED -
O/P LVDS O/P
41
TXEC+
O/P LVDS O/P
42
TXEC -
O/P LVDS O/P
43
TXEB+
O/P LVDS O/P
44
TXEB -
O/P LVDS O/P
13
Description
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
Power supply for digital circuitry
Ground pin for digital circuitry
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
LVTTL level data input
Power supply for PLL circuitry
Ground pin for PLL circuitry
Ground pin for PLL circuitry
Power supply for PLL circuitry
Power supply for logic
Ground pin for logic
LVTTL level data clock input
Power supply for digital circuitry
Ground pin for digital circuitry
Powerdown Bar (Active LOW)
0 = DEVICE DISABLED
1 = DEVICE ENABLED
Two-wire Serial interface - clock
Two-wire Serial interface - data
Rising Falling Bar (Figure 10)
0 = FALLING EDGE
1 = RISING EDGE
“EVEN” bank enable
0 = LVDS EVEN OUTPUTS DISABLED
1 = LVDS EVEN OUTPUTS ENABLED
Power supply for analog circuitry
Ground pin for analog circuitry
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
www.national.com