DS90C3201_06 Datasheet, PDF (17/20 Pages) National Semiconductor (TI) – 3.3V 8 MHz to 135MHz Dual FPD-LIink Transmitter

DS90C3201 Two-Wire Serial Interface Register Table
Address
0d/0h
1d/1h
2d/2h
3d/3h
4d/4h
5d/5h
6d/6h
7d/7h
8d/8h
9d/9h
10d/ah
11d/bh
R/W
R
R
R
R
R
R
R
R
R
R
R
R
RESET
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
Bit #
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Description
Vender ID low byte[7:0] = 05h
Vender ID high byte[15:8] =13h
Device ID low byte[7:0] = 27h
Device ID high byte 15:8] = 67h
Device revision [7:0] = 00h to begin with
Low frequency limit, 8Mhz = 8h
High frequency limit 135Mhz = 87h =
0000_0000_1000_0111
Reserved
Reserved
Reserved
Reserved
Reserved
Default Value
0000_0101
0001_0011
0010_0111
0110_0111
0000_0000
0000_1000
1000_0111
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
20d/14h
R/W
PWDN
[7:0] Reserved
0000_0000
21d/15h
R/W
PWDN
[7:0] Reserved
0000_0000
22d/16h
R/W
PWDN
[7:0] Reserved
0000_0000
23d/17h
R/W
PWDN
[7:0] Reserved
0000_0000
24d/18h
R/W
PWDN
[7:0] Reserved
0000_0000
25d/19h
R/W
PWDN
[7:0] Reserved
0000_0000
26d/1ah
R/W
PWDN
[7:3] Reserved
0000_0000
[2:0] LVTTL input delay control for TCLK channel, 000 is
Default which means no delays add to TCLK, two buffer
delay per step adjustment for Tsetup; while single buffer
step adjustment for Thold
[111]: move internal clock early by 4 buffer delays
(increases setup time)
[110]: move internal clock early by 3 buffer delays
(increases setup time)
[101]: move internal clock early by 2 buffer delays
(increases setup time)
[100]: move internal clock early by 1 buffer delays
(increases setup time)
[001]: move internal clock late by 2 buffer delays
(increases hold time)
[010]: move internal clock late by 4 buffer delays
(increases hold time)
[011]: move internal clock late by 6 buffer delays
(increases hold time)
[000]: Default
27d/1bh
R/W
PWDN
[7:0] Reserved
0000_0000
17
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