DS92LV0411 Datasheet, PDF (7/40 Pages) National Semiconductor (TI) – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

Pin Name
Pin #
I/O, Type Description
Optional Serial Bus Control
ID[x]
12
I, Analog Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See .
SCL
5
I, LVCMOS Serial Control Bus Clock Input - Optional
Open Drain SCL requires an external pull-up resistor to 3.3V.
SDA
4
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor 3.3V.
Power and Ground
VDDL
6, 31
Power Logic Power, 1.8 V ±5%
VDDA
38, 43
Power Analog Power, 1.8 V ±5%
VDDP
6
Power PLL Power, 1.8 V ±5%
VDDSC
46, 47
Power SSC Generator Power, 1.8 V ±5%
VDDTX
24
Power Channel Link LVDS Parallel Output Power, 1.8 V ±5%
VDDIO
25
Power LVCMOS I/O Power and Channel Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
GND
9, 14, 26, 32,
39, 44, 45, 48
Ground Ground
DAP
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
NOTE: 1= HIGH, 0 L= LOW
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
7
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