DS92LV0411 Datasheet, PDF (26/40 Pages) National Semiconductor (TI) – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

TABLE 9. SSCG Configuration (LF_MODE = H) — Des Output
SSC[3:0] Inputs
LF_MODE = H (5 — 20 MHz)
SSC3
SSC2
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
SSC1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
SSC0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Result
fdev (%)
N/A
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
fmod (kHz)
CLK/620
CLK/370
CLK/258
CLK/192
30125273
FIGURE 24. SSCG Waveform
Power Saving Features
Des — Power Down Feature (PDB)
The DS92LV0412 has a PDB input pin to ENABLE or POWER
DOWN the device. This pin is controlled by the host and is
used to save power, disabling the Des when the display is not
needed. An auto detect mode is also available. In this mode,
the PDB pin is tied HIGH and the Des will enter POWER
DOWN when the serial stream stops. When the serial stream
starts up again, the Des will lock to the input stream and assert
the LOCK pin and output valid data. In the POWER DOWN
mode, the LVDS data and clock output states are determined
by the OSS_SEL status. Note – in POWER DOWN, the op-
tional Serial Bus Control Registers are RESET.
Des — Stop Stream SLEEPFeature
The DS92LV0412 will enter a low power SLEEP state when
the input serial stream is stopped. A STOP condition is de-
tected when the embedded clock bits are not present. When
the serial stream starts again, the Des will then lock to the
incoming signal and recover the data. Note – in STOP CLOCK
SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
1.8V or 3.3V VDDIO Operation
The DS92LV0412 parallel control bus can operate with 1.8 V
or 3.3 V levels (V_DDIO) for host compatibility. The 1.8 V levels
will offer a system power savings.
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