English
Language : 

DS92LV0411 Datasheet, PDF (36/40 Pages) National Semiconductor (TI) – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface
TABLE 15. Deserializer Alternate Color / Data Mapping
Channel Link
TxOUT3
TxOUT2
TxOUT1
TxOUT0
Bit Number
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
RGB (LSB
Example)
B1
B0
G1
G0
R1
R0
DE
VS
HS
B7
B6
B5
B4
B3
B2
G7
G6
G5
G4
G3
G2
R7
R6
R5
R4
R3
R2
DS92LV0412
Settings
MAPSEL = 0
DS92LV2411 DS90UR241 DS99R421Q DS90C241
B1
B0
G1
G0
R1
R0
DE
VS
HS
B7
B6ROUT10
B5
B4
B3
B2
G7
G6
G5
G4
G3
G2
R7
R6
R5
R4
R3
R2
N/A
CONFIG [1:0] = 00
N/A
DIN20
RxIN2
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
RxIN1
DIN12
DIN11
DIN10
DIN9
DIN8
DIN7
DIN6
RxIN0
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
DIN923
OS2
DIN922
OS1
DIN921
OS0
CONFIG [1:0] = 10
DIN20
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
DIN11
DIN10
DIN9
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
DIN923
DIN922
DIN921
CONFIG [1:0] = 11
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS devices should
be designed to provide low-noise power feed to the device.
Good layout practice will also separate high frequency or
high-level inputs and outputs to minimize unwanted stray
noise pickup, feedback and interference. Power system per-
formance may be greatly improved by using thin dielectrics (2
to 4 mils) for power / ground sandwiches. This arrangement
provides plane capacitance for the PCB power system with
low-inductance parasitics, which has proven especially effec-
tive at high frequencies, and makes the value and placement
of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum elec-
trolytic types. RF capacitors may use values in the range of
0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF
to 10 uF range. Voltage rating of the tantalum capacitors
should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low fre-
quency switching noise. It is recommended to connect power
and ground pins directly to the power and ground planes with
bypass capacitors connected to the plane with via on both
ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the
path.
A small body size X7R chip capacitor, such as 0603, is rec-
ommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz. To provide ef-
fective bypassing, multiple capacitors are often used to
achieve low impedance between the supply rails over the fre-
quency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switch-
www.national.com
36