DS92LV0411 Datasheet, PDF (4/40 Pages) National Semiconductor (TI) – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

Pin Name
Pin #
I/O, Type Description
VODSEL
20
I, LVCMOS Differential Driver Output Voltage Select — Pin or Register Control
w/ pull-down VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typ)
De-Emph
19
I, Analog De-Emphasis Control — Pin or Register Control
w/ pull-up De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See Table 4
MAPSEL
26
I, LVCMOS Channel Link Map Select — Pin or Register Control
w/ pull-down MAPSEL = 1, MSB on RxIN3+/-. Figure 22
MAPSEL = 0, LSB on RxIN3+/-. Figure 21
CONFIG
[1:0]
10, 9
I, LVCMOS Operating Modes — Pin or Limited Register Control
w/ pull-down Determines the device operating mode and interfacing device. Table 1
CONFIG[1:0] = 00: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG [1:0] = 11: Interfacing to DS90C124
ID[x]
4
I, Analog Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 10.
SCL
SDA
BISTEN
6
I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V_DDIO.
7
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor V_DDIO.
21
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES[7:0]
25, 3, 36, 27, I, LVCMOS Reserved - tie LOW
18, 13, 12, 8 w/ pull-down
Channel Link II Serial Interface
DOUT+
16
O, CML True Output.
The output must be AC Coupled with a 0.1 μF capacitor.
DOUT-
15
O, CML Inverting Output.
The output must be AC Coupled with a 0.1 μF capacitor.
Power and Ground
VDDL
5
Power Logic Power, 1.8 V ±5%
VDDP
11
Power PLL Power, 1.8 V ±5%
VDDHS
14
Power TX High Speed Logic Power, 1.8 V ±5%
VDDTX
17
Power Output Driver Power, 1.8 V ±5%
VDDRX
24
Power RX Power, 1.8 V ±5%
VDDIO
22
Power LVCMOS I/O Power and Channel Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
NOTE: 1= HIGH, 0 L= LOW
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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