DS92LV0411 Datasheet, PDF (31/40 Pages) National Semiconductor (TI) – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

TABLE 13. DS92LV0412 DESERIALIZER — Serial Bus Control Registers
ADD ADD Register Name Bit(s)
(dec) (hex)
0 0 Des Config 1
7
R/W
R/W
Defa Function
ult
(bin)
0 LFMODE
6 R/W 0 MAPSEL
5 R/W 0 Reserved
4 R/W 0 Reserved
3:2 R/W 00 CONFIG
1 1 Device ID
1 R/W 0 SLEEP
0 R/W 0 REG Control
7 R/W 0 REG ID
6:0 R/W 1110 ID[X]
000
2 2 Des Features 1 7 R/W 0 OEN
6 R/W 0 OSS_SEL
5:4 R/W 00 Reserved
3 R/W 0 VODSEL
2:0 R/W 000 OSC_SEL
Description
SSCG Mode — low frequency support
0: 20 to 65 MHz Operation
1: 10 to 20 MHz Operation
Channel Link Map Select
0: LSB on TxOUT3+/-
1: MSB on TxOUT3+/-
Reserved
Reserved
00: Control Signal Filter Disabled
01: Control Signal Filter Enabled
10: Reserved
11: Reserved
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0: Configurations set from control pins
1: Configuration set from registers (except I2C_ID)
0: Address from ID[X] Pin
1: Address from Register
Serial Bus Device ID, IDs are:
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
All other addresses are Reserved.
Output Enable Input
Table 5
Output Sleep State Select
Table 5
Reserved
LVDS Driver Output Voltage Select
0: LVDS VOD is ±250 mV, 500 mVp-p (typ)
1: LVDS VOD is ±400 mV, 800 mVp-p (typ)
000: OFF
001:RESERVED
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3MHz ±40%
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