DS92LV0411 Datasheet, PDF (25/40 Pages) National Semiconductor (TI) – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

EMI Reduction Features
Des — VOD Select (VODSEL)
The differential output voltage of teh Channel Link interface
is controlled by the VODSEL input.
TABLE 7. Des — Differential Output
Voltage Table
VODSEL Result
L
VOD is 250 mV TYP (500 mVp-p)
H
VOD is 400 mV TYP (800 mVp-p)
Des — SSCG Generation — Optional
The Des provides an internally generated spread spectrum
clock (SSCG) to modulate its outputs. Both clock and data
outputs are modulated. This will aid to lower system EMI.
Output SSCG deviations to ±2% (4% total) at up to 100 kHz
modulations is available. See Table . This feature may be
controlled by external STRAP pins or by register.
TABLE 8. SSCG Configuration (LF_MODE = L) — Des Output
SSC[3:0] Inputs
LF_MODE = L (20 — 55 MHz)
SSC3
SSC2
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
SSC1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
SSC0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Result
fdev (%)
N/A
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
fmod (kHz)
CLK/2168
CLK/1300
CLK/868
CLK/650
25
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