DS92LV0411 Datasheet, PDF (5/40 Pages) National Semiconductor (TI) – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0412 Pin Diagram
DS92LV0412 — Top View
30125271
DS92LV0412 Pin Descriptions
Pin Name
Pin #
I/O, Type
Channel Link II Serial Interface
RIN+
40
I, CML
RIN-
41
I, CML
Channel Link Parallel Output Interface
RxIN[3:0]+ 15, 19, 21, 23 O, LVDS
RxIN[3:0]- 16, 20, 22, 24 O, LVDS
RxCLKIN+
17
O, LVDS
RxCLKIN-
18
O, LVDS
Description
True Input.
The output must be AC Coupled with a 0.1 μF capacitor.
Inverting Input.
The output must be AC Coupled with a 0.1 μF capacitor.
True LVDS Data Output
This pair should have a 100 Ω termination for standard LVDS levels.
Inverting LVDS Data Output
This pair should have a 100 Ω termination for standard LVDS levels.
True LVDS Clock Output
This pair should have a 100 Ω termination for standard LVDS levels.
Inverting LVDS Clock Output
This pair should have a 100 Ω termination for standard LVDS levels.
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