DS92LV1021 Datasheet, PDF (6/18 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_RFCP
t_RFDC
t_RFCP /
t_TCP
t_RFTT
REFCLK Period
REFCLK Duty Cycle
Ratio of REFCLK to
TCLK Periods
REFCLK Transition Time
25
T
50
0.83
1
3
Max
Units
62.5
ns
%
1.03
6
ns
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
t_RCP
Receiver out Clock
Period
Figure 9
t_RCP = t_TCP
RCLK
25
t_CLH
CMOS/TTL Low-to-High CL = 15 pF
Rout(0-9),
2
Transition Time
Figure 4
t_CHL
CMOS/TTL High-to-Low
Transition Time
LOCK,
2
RCLK
t_DD
t_ROS
Deserializer Delay
ROUT (0-9) Setup Data
to RCLK
Figure 10
Figure 11
RCLK
1.75*t_RCP
0.4*t_RCP
1.75*t_RCP+3
0.5*t_RCP
t_ROH
ROUT (0-9) Hold Data
to RCLK
−0.4*t_RCP
−0.5*t_RCP
t_RDC
t_HZR
RCLK Duty Cycle
HIGH to TRI-STATE
Delay
Figure 12
40
Rout(0-9),
LOCK
50
4+0.5*t_RCP
t_LZR
LOW to TRI-STATE
Delay
4.2+0.5*t_RCP
t_ZHR
TRI-STATE to HIGH
Delay
6+0.5*t_RCP
t_ZLR
TRI-STATE to LOW
Delay
6.5+0.5*t_RCP
t_DSR1 Deserializer PLL Lock (Note 5)
16MHz
7
Time from PWRDWN Figure 13
(with SYNCPAT)
Figure 14
40MHz
4.8
t_DSR2
Deserializer PLL Lock
time from SYNCPAT
16MHz
7
40MHz
4.5
t_ZHLK
TRI-STATE to HIGH
Delay (power-up)
LOCK
1.5
t_RNM
Deserializer Noise
Margin
Figure 15
(Note 6)
16 MHz
400
40 MHz
100
1100
400
Max
62.5
5
5
1.75*t_RCP+7
60
10+t_RCP
10+t_RCP
12+t_RCP
12+t_RCP
15
25.6
10
7
12
Units
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
µs
µs
µs
µs
ns
ps
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions
of the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is the time
required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before
initiating either condition. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change
from not receiving data to receiving synchronization patterns (SYNCPATs).
Note 6: tRNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur.
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