DS92LV1021 Datasheet, PDF (15/18 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

Serializer Pin Description
Pin Name
DIN
TCLK_R/F
DO+
DO−
DEN
PWRDN
TCLK
SYNC
DVCC
DGND
AVCC
AGND
I/O
No.
Description
I
3–12
Data Input. TTL levels inputs. Data on these pins are loaded into a
10-bit input register.
I
13
Transmit Clock Rising/Falling strobe select. TTL level input. Selects
TCLK active edge for strobing of DIN data. High selects rising
edge. Low selects falling edge.
O
22
+ Serial Data Output. Non-inverting Bus LVDS differential output.
O
21
− Serial Data Output. Inverting Bus LVDS differential output.
I
19
Serial Data Output Enable. TTL level input. A low, puts the Bus
LVDS outputs in TRI-STATE.
I
24
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode. Do not float the PWRDWN pin, external pull resistor is
recommended. A pull-down will disable the device until it is actively
driven (enabled).
I
14
Transmit Clock. TTL level input. Input for 16 MHz–40 MHz
(nominal) system clock.
I
1, 2
Assertion of SYNC (high) for at least 1024 synchronization symbols
to be transmitted on the Bus LVDS serial output. Synchronization
symbols continue to be sent if SYNC continues asserted. TTL level
input. The two SYNC pins are ORed.
I
27, 28
Digital Circuit power supply.
I
15, 16
Digital Circuit ground.
I
17, 26
Analog power supply (PLL and Analog Circuits).
I
18, 25, 20, 23 Analog ground (PLL and Analog Circuits).
15
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