DS92LV1021 Datasheet, PDF (12/18 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

AC Timing Diagrams and Test Circuits (Continued)
SW - Setup and Hold Time (Internal data sampling window)
t_JIT- Serializer Output Bit Position Jitter
t_RSM = Receiver Sampling Margin Time
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FIGURE 15. Receiver Bus LVDS Input Skew Margin
V_OD = (DO⁺)–(DO^−).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
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