DS92LV1021 Datasheet, PDF (2/18 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

Block Diagrams (Continued)
Application
Functional Description
The DS92LV1021 and DS92LV1210 is a 10-bit Serializer /
Deserializer chipset designed to transmit data over a heavily
loaded differential backplanes at clock speeds from 16 to
40MHz. It may also be used to drive data over Unshielded
Twisted Pair (UTP) cable.
The chipset has three active states of operation: Initializa-
tion, Data Transfer, and Resynchronization; and two passive
states: Powerdown and TRI-STATE^®.
The following sections describe each operation and passive
state.
Initialization
Before data can be transferred both devices must be initial-
ized. Initialization refers to synchronization of the Serializer
and the Deserializer PLL’s to local clocks that may be the
same or separate. Afterward, synchronization of Deserializer
to Serializer occurs as the second step of initialization.
Step 1: When V_CC is applied to both Serializer and/or Dese-
rializer, the respective outputs are held in TRI-STATE^® and
internal circuitry is disabled by on-chip power-on circuitry.
When V_CC reaches V_CC OK (2.5V) the PLL in each device
begins locking to a local clock. For the Serializer, the local
clock is the transmit clock, TCLK, provided by the source
ASIC or other device. For the Deserializer, the local clock is
provided by an on-board oscillator or other source and ap-
plied to the REFCLK pin. After V_CC OK is reached the
device’s PLL will lock.
The Serializer outputs are held in TRI-STATE while the PLL
locks to the TCLK. The Serializer is now ready to send data
or SYNC patterns depending on the levels of the SYNC1 and
SYNC2 inputs. The SYNC pattern is composed of six ones
and six zeros switching at the input clock rate.
The Deserializer LOCK output will remain high while its PLL
is locking to the local clock- the REFCLK input and then to
SYNC patterns on the input.
Step 2: The Deserializer PLL must synchronize to the Seri-
alizer to complete the initialization. The transmission of
SYNC patterns to the Deserializer enables the Deserializer
to lock to the Serializer signal.
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Control of the sync pins is left to the user. A feedback loop
between the LOCK pin is one recommendation. Another
option is that one or both of the Serializer SYNC inputs are
asserted for at least 1024 cycles of TCLK to initiate trans-
mission of SYNC patterns. The Serializer will continue to
send SYNC patterns after the minimum of 1024 if either of
the SYNC inputs remain high.
When the Deserializer detects edge transitions at the Bus
LVDS input it will attempt to lock to the embedded clock
information. When the Deserializer locks to the Bus LVDS
clock, the LOCK output will go low. When LOCK is low the
Deserializer outputs represent incoming Bus LVDS data.
Data Transfer
After initialization, the Serializer inputs DIN0–DIN9 may be
used to input data to the Serializer. Data is clocked into the
Serializer by the TCLK input. The edge of TCLK used to
strobe in data is selectable via the TCLK_R/F pin. TCLK_R/F
high selects the rising edge for clocking data and low selects
the falling edge. If either of the SYNC inputs is high for
5*TCLK cycles the data at DIN 0-DIN9 is ignored regardless
of the clock edge.
A start bit and a stop bit, appended internally, frame the data
bits in the register. The start bit is always high and the stop
bit is always low. The start and stop bits function as the
embedded clock bits in the serial stream.
Serialized data and clock bits (10+2 bits) are transmitted
from the serial data output (DO) at 12 times the TCLK
frequency. For example, if TCLK is 40 MHz, the serial rate is
40 x 12 = 480 Mega bits per second. Since only 10 bits are
from input data, the serial “payload” rate is 10 times the
TCLK frequency. For instance, if TCLK = 40 MHz, the pay-
load data rate is 40 x 10 = 400 Mbps. TCLK is provided by
the data source and must be in the range 16 MHz to 40 MHz
nominal.
The outputs (DO±) can drive a heavily loaded backplane or
a point-to-point connection. The outputs transmit data when
the enable pin (DEN) is high, PWRDN = high and SYNC1
and SYNC2 are low. The DEN pin may be used to TRI-
STATE the outputs when driven low.
The LOCK pin on the Deserializer is driven low when it is
synchronized with the Serializer. The Deserializer locks to
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