DS92LV1021 Datasheet, PDF (13/18 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

Application Information
USING THE DS92LV1021 AND DS92LV1210
The Serializer and Deserializer chipset is an easy to use
transmitter and receiver pair that sends 10 bits of parallel
TTL data over a serial Bus LVDS link up to 400 Mbps.
Serialization of the input data is accomplished using an
onboard PLL at the Serializer which embeds two clock bits
with the data. The Deserializer uses a separate reference
clock (REFCLK) and an onboard PLL to extract the clock
information from the incoming data stream and deserialize
the data. The Deserializer monitors the incoming clock infor-
mation to determine lock status and will indicate loss of lock
by raising the LOCK output.
POWER CONSIDERATIONS
All CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the Bus LVDS outputs minimize the
slope of the speed vs. I_CC curve of CMOS designs.
POWERING UP THE SERIALIZER
The DS92LV1021 must be powered up using a specific
sequence to properly start the PLL up. Not following the
sequence can cause the Bus LVDS outputs to be stuck in a
certain output state. This may occur if the TCLK input is
driven before power is applied to the Serializer. It is impor-
tant to note that this is not a latch up condition: no excessive
current is drawn by the Serializer in this state and the power
does not need to be cycled to recover from this state. Cycling
the PWRDWN pin from high to low and back to high will reset
the PLL and return the Serializer to normal operation.
To avoid this condition, the Serializer should be powered up
(ALL V_CC pins) simultaneously with the PWRDWN pin held
low for 1µs. Do not float the PWRDWN pin, external pull
resistor is recommended. Once the V_CC pins have stabilized
the TCLK input can be driven and the Serializer will be ready
for data transmission.
POWERING UP THE DESERIALIZER
The DS92LV1210 can be powered up at any time following
the proper sequence. The REFCLK input can be running
before the Deserializer is powered up and it must be running
in order for the Deserializer to lock to incoming data. The
Deserializer outputs will remain in TRI-STATE™ until the
Deserializer detects data transmission at its inputs and locks
to the incoming stream. The recommended power up se-
quence for the deserializer is to power up all V_CC pins
simultaneously with the PWRDWN pin held low for 1µs.
Once the V_CC pins have stabilized the Deserializer is ready
for locking. Another option to ensure proper power up is to
cycle the PWRDWN pin from high to low and back to high
after power up.
TRANSMITTING DATA
Once the Serializer and Deserializer are powered up and
running they must be phase locked to each other in order to
transmit data. Phase locking is accomplished by the Serial-
izer sending SYNC patterns to the Deserializer. SYNC pat-
terns are sent by the Serializer whenever SYNC1 or SYNC2
inputs are held high. The LOCK output of the Deserializer is
high whenever the Deserializer is not locked. Connecting the
LOCK output of the Deserializer to one of the SYNC inputs of
the Serializer will guarantee that enough SYNC patterns are
sent to achieve Deserializer lock.
While the Deserializer LOCK output is low, data at the De-
serializer outputs (ROUT0-9) is valid except for the specific
case of loss of lock during transmission.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic
factors include:
Serializer: TCLK jitter, V_CC noise (noise bandwidth and
out-of-band noise)
Media: ISI, V_CM noise
Deserializer: V_CC noise
RECOVERING FROM LOCK LOSS
In the case where the Serializer loses lock during data
transmission up to 5 cycles of data that was previously
received can be invalid. This is due to the delay in the lock
detection circuit. The lock detect circuit requires that invalid
clock information be received 4 times in a row to indicate
loss of lock. Since clock information has been lost it is
possible that data was also lost during these cycles. When
the Deserializer LOCK pin goes low, data from at least the
previous 5 cycles should be resent upon regaining lock.
Lock can be regained at the Deserializer by causing the
Serializer to resend SYNC patterns as described above.
PCB CONSIDERATIONS
The Bus LVDS devices Serializer and Deserializer should be
placed as close to the edge connector as possible. In mul-
tiple Deserializer applications, the distance from the Deseri-
alizer to the slot connector appears as a stub to the Serial-
izer driving the backplane traces. Longer stubs lower the
impedance of the bus increasing the load on the Serializer
and lowers threshold margin at the Deserializers. Deserial-
izer devices should be placed no more than 1 inch from the
slot connector.
TRANSMISSION MEDIA
The Serializer and Deserializer are designed for data trans-
mission over a multi-drop bus. Multi-drop buses use a single
Serializer and multiple Deserializer devices. Since the Seri-
alizer can be driving from any point on the bus, the bus must
be terminated at both ends. For example, a 100 Ohm differ-
ential bus must be terminated at each end with 100 Ohms
lowering the DC impedance that the Serializer must drive to
50 Ohms. This load is further lowered by the addition of
multiple Deserializers. Adding up to 20 Deserializers to the
bus (depending upon spacing) will lower the total load to
about 27 Ohms (54 Ohm bus). The Serializer is designed for
DC loads between 27 and 100 Ohms.
The Serializer and Deserializer can also be used in point-to-
point configuration of a backplane, PCB trace or through a
twisted pair cable. In point-to-point configurations the trans-
mission media need only be terminated at the receiver end.
In the point-to-point configuration the potential of offsetting
the ground levels of the Serializer vs. the Deserializer must
be considered. Bus LVDS provides a plus / minus one volt
common mode range at the receiver inputs.
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