DS92LV1021 Datasheet, PDF (10/18 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

AC Timing Diagrams and Test Circuits (Continued)
Timing shown for RCLK_R/F = LOW
Duty Cycle (t_RDC) =
10011013
FIGURE 11. Deserializer Setup and Hold Times
FIGURE 12. Deserializer TRI-STATE Test Circuit and Timing
10011014
www.national.com
10