DS92LV1021 Datasheet, PDF (16/18 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

Deserializer Pin Description
Pin Name
ROUT
RCLK_R/F
RI+
RI−
PWRDN
LOCK
RCLK
REN
DVCC
DGND
AVCC
AGND
REFCLK
I/O
No.
Description
O
15–19, 24–28 Data Output. ±9 mA CMOS level outputs.
I
2
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High selects
rising edge. Low selects falling edge.
I
5
+ Serial Data Input. Non-inverting Bus LVDS differential input.
I
6
− Serial Data Input. Inverting Bus LVDS differential input.
I
7
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
O
10
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wire OR connection.
O
9
Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
I
8
Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9,
LOCK and RCLK when driven low.
I
21, 23
Digital Circuit power supply.
I
14, 20, 22 Digital Circuit ground.
I
4, 11
Analog power supply (PLL and Analog Circuits).
I
1, 12, 13
Analog ground (PLL and Analog Circuits).
I
3
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
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