DS90CR483A Datasheet, PDF (6/24 Pages) Texas Instruments – DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz

Chipset RSKM Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 4, 7). See Applications Informa-
tion section for more details on this parameter and how to apply it.
Symbol
Parameter
Min
Typ
Max
Units
RSKM Receiver Skew Margin without Deskew f = 112 MHz
170
ps
in non-DC Balance Mode, (Figure 13), _{f = 100 MHz}
170
240
ps
(Note 5)
f = 85MHz
300
350
ps
f = 66MHz
300
350
ps
RSKM Receiver Skew Margin without Deskew f = 112 MHz
170
ps
in DC Balance Mode, (Figure 13),
f = 100 MHz
170
200
ps
(Note 5)
f = 85 MHz
250
300
ps
f = 66 MHz
250
300
ps
f = 50MHz
300
350
ps
RSKMD Receiver Skew Margin with Deskew in f = 33 to 80 MHz 0.25TBIT
ps
DC Balance, (Figure 14),
(Note 6)
RDR
Receiver Deskew Range
f = 80 MHz
±1
TBIT
RDSS
Receiver Deskew Step Size
f = 80 MHz
0.3TBIT
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 3.3V and T _A = +25°C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V_TH, V_TL, V_OD and ΔV_OD).
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is
functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested to verify functional
performance.
Note 5: Receiver Skew Margin (RSKM) is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse
positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew,
inter-symbol interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle, TJCC) + ISI (if any). See Applications Information section for more details.
Note 6: Receiver Skew Margin with Deskew (RSKMD) is defined as the valid data sampling region at the receiver inputs. The DESKEW function will constrain
the receiver’s sampling strobes to the middle half of the LVDS bit and removes (adjusts for) fixed interconnect skew. This margin (RSKMD) allows for inter-symbol
interference (dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance, and LVDS clock jitter (TJCC).
RSKMD ≥ ISI + TPPOS(variance) + source clock jitter (cycle to cycle). See Applications Information section for more details.
Note 7: Typical values for RSKM and RSKMD are applicable for fixed V_CC and T _A for the Transmitter and Receiver (both are assumed to be at the same V_CC
and T _A points).
Note 8: TJCC is a function of input clock quality and also PLLVCC noise. At 112MHz operation, with a +/−300ps input impulse at a 2us rate, TJCC has been
measured to be in the 70-80ps range (<100ps). With a nominal input clock quality (no input impulse jitter, jitter < 500kHz), TJCC is typically 50ps or less. For
RSKM/RSKMD calculations 100ps is typically used as the TJCC budget. See Clock Jitter discussion in the Applications Information section of this datasheet for
further information.
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