DS90CR483A Datasheet, PDF (14/24 Pages) Texas Instruments – DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz

Applications Information
The DS90CR483A and DS90CR484A are upgrades to the
DS90CR483 and DS90CR484. The DS90CR483A/
DS90CR484A no longer have a PLL auto gear option se-
lectable via the PLLSEL pin. The PLLSEL pin now allows for
the PLL low gear only or high gear only to be selected. The
DS90CR483A/DS90CR484A are fully compatible with older
generation Channel Link devices. It should be noted that
whenever devices with the auto gear feature are used, an
unintentional gear shift caused by fluctuations in V_CC may
cause bit errors. By removing the auto gear feature in the
DS90CR483A/DS90CR484A, the potential for any gear shift
related bit errors has been eliminated.
The DS90CR483A/DS90CR484A chipset is improved over
prior generations of Channel Link devices and offers higher
bandwidth support and longer cable drive with three areas of
enhancement. To increase bandwidth, the maximum clock
rate is increased to 112 MHz and 8 serialized LVDS outputs
are provided. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. This re-
quires the use of one pull up resistor to Vcc; please refer to
to set the level needed. Optional DC balancing on a cycle-to-
cycle basis, is also provided to reduce ISI (Inter-Symbol In-
terference). With pre-emphasis and DC balancing, a low
distortion eye-pattern is provided at the receiver end of the
cable. A cable deskew capability has been added to deskew
long cables of pair-to-pair skew of up to ±1 LVDS data bit time
(up to 80 MHz clock rates). For details on deskew, refer to
“Deskew” section below. These three enhancements allow
cables 5+ meters in length to be driven depending upon me-
dia and clock rate.
The DS90CR483A/DS90CR484A chipset may also be used
in a non-DC Balance mode. In this mode pre-emphasis is
supported. In this mode, the chipset is also compatible with
21 and 28-bit Channel Link Receivers. See for the LVDS
mapping.
NEW FEATURES DESCRIPTION
1. Pre-emphasis
Pre-emphasis adds extra current during LVDS logic transition
to reduce the cable loading effects. Pre-emphasis strength is
set via a DC voltage level applied from min to max (0.75V to
Vcc) at the “PRE” pin. A higher input voltage on the ”PRE” pin
increases the magnitude of dynamic current during data tran-
sition. The “PRE” pin requires one pull-up resistor (Rpre) to
Vcc in order to set the DC level. There is an internal resistor
network, which cause a voltage drop. Please refer to the ta-
bles below to set the voltage level.
The waveshape at the Receiver input should not exhibit over
or undershoot with the proper amount of pre-emphasis set.
Too much pre-emphasis generates excess noise and in-
creases power dissipation. Cables less than 2 meters in
length typically do not require pre-emphasis.
TABLE 1. Pre-emphasis DC voltage level with (Rpre)
Rpre
1MΩ or NC
50kΩ
9kΩ
3kΩ
1kΩ
100Ω
Resulting PRE Voltage
0.75V
1.0V
1.5V
2.0V
2.6V
Vcc
Effect
Standard LVDS
50% pre-emphasis
100% pre-emphasis
TABLE 2. Pre-emphasis needed per cable length
Frequency
112MHz
112MHz
80MHz
80MHz
66MHz
PRE Voltage
1.0V
1.5V
1.0V
1.2V
1.5V
Typical cable length
2 meters
5 meters
2 meters
5+ meters
7 meters
Note 10: This is based on testing with standard shield twisted pair cable. The amount of pre-emphasis will vary depending on the type of cable, length and
operating frequency.
2. DC Balance
word disparity shall be calculated as a continuous sum of all
In addition to data information an additional bit is transmitted
on every LVDS data signal line during each cycle as shown
in . This bit is the DC balance bit (DCBAL). The purpose of
the DC Balance bit is to minimize the short- and long-term DC
bias on the signal lines. This is achieved by selectively send-
the modified data disparity values, where the unmodified data
disparity value is the calculated data disparity minus 1 if the
data is sent unmodified and 1 plus the inverse of the calcu-
lated data disparity if the data is sent inverted. The value of
the running word disparity shall saturate at +7 and −6.
ing the data either unmodified or inverted.
The value of the DC balance bit (DCBAL) shall be 0 when the
The value of the DC balance bit is calculated from the running
word disparity and the data disparity of the current word to be
sent. The data disparity of the current word shall be calculated
by subtracting the number of bits of value 0 from the number
of bits value 1 in the current word. Initially, the running word
disparity may be any value between +7 and −6. The running
data is sent unmodified and 1 when the data is sent inverted.
To determine whether to send data unmodified or inverted,
the running word disparity and the current data disparity are
used. If the running word disparity is positive and the current
data disparity is positive, the data shall be sent inverted. If the
running word disparity is positive and the current data dispar-
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