DS90CR483A Datasheet, PDF (19/24 Pages) Texas Instruments – DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz

DS90CR484A Pin Descriptions—Channel Link Receiver
Pin Name
RxINP
RxINM
RxOUT
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
DESKEW
PD
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
NC
I/O
Description
I
Positive LVDS differential data inputs.
I
Negative LVDS differential data inputs.
O
TTL level data outputs. In PowerDown (PD = Low) mode, receiver outputs are forced to a Low
state.
I
Positive LVDS differential clock input.
I
Negative LVDS differential clock input.
O
TTL level clock output. The rising edge acts as data strobe.
I
PLL range select. This pin should be tied to V_CC for high-range. Tied to ground or NC will force
the PLL to low range only. Low range is 33 — 40 MHz. High range is 38 — 112 MHz.(Note 11)
I
Deskew / Oversampling “on/off” select. When using the Deskew / Oversample feature this pin
must be tied to V_CC. Tieing this pin to ground disables this feature. (Note 11) Deskew is only
supported in the DC Balance mode.
I
TTL level input. When asserted (low input) the receiver outputs are Low. (Note 11)
I
Power supply pins for TTL outputs and digital circuitry. Bypass not required on Pins 6 and 77.
I
Ground pins for TTL outputs and digital circuitry.
I
Power supply for PLL circuitry.
I
Ground pin for PLL circuitry.
I
Power supply pin for LVDS inputs.
I
Ground pins for LVDS inputs.
No Connect. Make NO Connection to these pins - leave open.
Note 12: These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under test conditions
receiver inputs will be in a HIGH state. If the cable interconnect (media) are disconnected which results in floating/terminated inputs, the outputs will remain in
the last valid state.
Note 13: The DS90CR484A is design to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90CR483A and deserialize the
LVDS data according to the define bit mapping.
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