DS90CR483A Datasheet, PDF (5/24 Pages) Texas Instruments – DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz

Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
LLHT
LVDS Low-to-High Transition Time, (Figure 2),
0.14
PRE = 0.75V (disabled)
LVDS Low-to-High Transition Time, (Figure 2),
0.11
PRE = Vcc (max)
LHLT
LVDS High-to-Low Transition Time, (Figure 2),
0.16
PRE = 0.75V (disabled)
LVDS High-to-Low Transition Time, (Figure 2),
0.11
PRE = Vcc (max)
TBIT
Transmitter Bit Width
1/7 TCIP
TPPOS Transmitter Pulse Positions - Normalized f = 33 to 70
−250
0
MHz
f = 70 to 112
−200
0
MHz
TJCC
Transmitter Jitter - Cycle-to-Cycle ((Note 8)
50
TCCS
TxOUT Channel to Channel Skew
40
TSTC
TxIN Setup to TxCLK IN, (Figure 5)
2.5
THTC
TxIN Hold to TxCLK IN, (Figure 5)
0
TPDL
Transmitter Propagation Delay - Latency, (Figure 7)
1.5(TCIP)+3.72 1.5(TCIP)+4.4
TPLLS Transmitter Phase Lock Loop Set, (Figure 9)
TPDD
Transmitter Powerdown Delay, (Figure 11)
Max
0.7
0.6
0.8
0.7
+250
+200
100
1.5(TCIP)+6.24
10
100
Units
ns
ns
ns
ns
ns
ps
ps
ps
ps
ns
ns
ns
ms
ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
CLHT
CMOS/TTL Low-to-High Transition Time, (Figure 3), Rx
data out
CMOS/TTL Low-to-High Transition Time, (Figure 3), Rx
clock out
CHLT
CMOS/TTL High-to-Low Transition Time, (Figure 3), Rx
data out
CMOS/TTL High-to-Low Transition Time, (Figure 3), Rx
clock out
RCOP RxCLK OUT Period, (Figure 6)
8.928
T
RCOH RxCLK OUT High Time, (Figure 6), f = 112 MHz
3.5
(Note 4)
f = 66 MHz
6.0
RCOL
RxCLK OUT Low Time, (Figure 6), f = 112 MHz
3.5
(Note 4)
f = 66 MHz
6.0
RSRC
RxOUT Setup to RxCLK OUT, (Figure f = 112 MHz
2.4
6), (Note 4)
f = 66 MHz
3.6
RHRC RxOUT Hold to RxCLK OUT, (Figure f = 112 MHz
3.4
6), (Note 4)
f = 66 MHz
7.0
RPDL
Receiver Propagation Delay - Latency, (Figure 8)
3(TCIP)+4.0
3(TCIP)+4.8
RPLLS Receiver Phase Lock Loop Set, (Figure 10)
RPDD
Receiver Powerdown Delay, (Figure 12)
Max
Units
2.0
ns
1.0
ns
2.0
ns
1.0
ns
30.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
3(TCIP)+6.5
ns
10
ms
1
µs
5
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