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DS90CR483A Datasheet, PDF (4/24 Pages) Texas Instruments – DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz
Symbol
Parameter
Conditions
LVDS DRIVER DC SPECIFICATIONS
|VOD|
Differential Output
Voltage
RL = 100Ω
ΔVOD
Change in VOD between
Complimentary Output
States
VOS
ΔVOS
Offset Voltage
Change in VOS between
Complimentary Output
States
IOS
Output Short Circuit
VOUT = 0V, RL = 100Ω
Current
IOZ
Output TRI-STATE
PD = 0V, VOUT = 0V or VCC
Current
LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential Input High VCM = +1.2V
Threshold
VTL
Differential Input Low
Threshold
IIN
Input Current
TRANSMITTER SUPPLY CURRENT
VIN = +2.4V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
ICCTW
Transmitter Supply
Current
Worst Case
RL = 100Ω, CL = 5 pF,
BAL = High,
Worst Case Pattern
(Figures 1, 2)
f = 33 MHz
f = 66 MHz
f = 112 MHz
ICCTZ
Transmitter Supply
Current
Power Down
PD = Low
Driver Outputs in TRI-STATE during power down
Mode
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current CL = 8 pF, BAL = High,
Worst Case
Worst Case Pattern
(Figures 1, 3)
f = 33 MHz
f = 66 MHz
f = 112 MHz
ICCRZ
Receiver Supply Current PD = Low
Power Down
Receiver Outputs stay low during power down mode.
Min
250
1.125
−100
Typ
345
1.25
−3.5
±1
91.4
106
155
5
125
200
250
20
Max Units
450
mV
35
mV
1.375
V
35
mV
−5
mA
±10
µA
+100 mV
mV
±10
µA
±10
µA
140
mA
160
mA
210
mA
50
µA
150
mA
210
mA
280
mA
100
µA
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
TCIT
TxCLK In Transition Time (Figure 4)
1.0
2.0
TCIP High TxCLK In Period, PLLSEL = High Gear (Figure 5)
8.928
T
TCIP Low TxCLK In Period, PLLSEL = Low Gear (Figure 5)
25
T
TCIH
TxCLK In High Time (Figure 5)
0.35T
0.5T
TCIL
TxCLK In Low Time (Figure 5)
0.35T
0.5T
TXIT
TxIN Transition Time
1.5
Max
3.0
26.3
30.3
0.65T
0.65T
6.0
Units
ns
ns
ns
ns
ns
ns
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