DS90CR483A Datasheet, PDF (1/24 Pages) Texas Instruments – DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz

April 4, 2008
DS90CR483A / DS90CR484A
48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz
General Description
The DS90CR483A transmitter converts 48 bits of CMOS/TTL
data into eight LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a ninth LVDS link. Every cycle
of the transmit clock 48 bits of input data are sampled and
transmitted. The DS90CR484A receiver converts the LVDS
data streams back into 48 bits of CMOS/TTL data. At a trans-
mit clock frequency of 112MHz, 48 bits of TTL data are
transmitted at a rate of 672Mbps per LVDS data channel. Us-
ing a 112MHz clock, the data throughput is 5.38Gbit/s (672M-
bytes/s).
The multiplexing of data lines provides a substantial cable re-
duction. Long distance parallel single-ended buses typically
require a ground wire per active signal (and have very limited
noise rejection capability). Thus, for a 48-bit wide data and
one clock, up to 98 conductors are required. With this Channel
Link chipset as few as 19 conductors (8 data pairs, 1 clock
pair and a minimum of one ground) are needed. This provides
an 80% reduction in cable width, which provides a system
cost savings, reduces connector physical size and cost, and
reduces shielding requirements due to the cables' smaller
form factor.
The 48 CMOS/TTL inputs can support a variety of signal
combinations. For example, 6 8-bit words or 5 9-bit (byte +
parity) and 3 controls.
The DS90CR483A/DS90CR484A chipset is improved over
prior generations of Channel Link devices and offers higher
bandwidth support and longer cable drive with three areas of
enhancement. To increase bandwidth, the maximum clock
rate is increased to 112 MHz and 8 serialized LVDS outputs
are provided. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. Option-
al DC balancing on a cycle-to-cycle basis, is also provided to
reduce ISI (Inter-Symbol Interference). With pre-emphasis
and DC balancing, a low distortion eye-pattern is provided at
the receiver end of the cable. A cable deskew capability has
been added to deskew long cables of pair-to-pair skew of up
to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These
three enhancements allow cables 5+ meters in length to be
driven.
The chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
For more details, please refer to the “Applications Informa-
tion” section of this datasheet.
Features
■ ^{Up to 5.38 Gbits/sec bandwidth}
■ ^{33 MHz to 112 MHz input clock support}
■ ^{LVDS SER/DES reduces cable and connector size}
■ ^{Pre-emphasis reduces cable loading effects}
■ ^{DC balance data transmission provided by transmitter}
reduces ISI distortion
■ ^{Cable Deskew of +/−1 LVDS data bit time (up to 80 MHz}
Clock Rate)
■ ^{5V Tolerant TxIN and control input pins}
■ ^{Flow through pinout for easy PCB design}
■ ^{+3.3V supply voltage}
■ ^{Transmitter rejects cycle-to-cycle jitter}
■ ^{Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard}
■ ^{Both devices are available in 100 lead TQFP package}
Generalized Block Diagrams
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