DS90CR483A Datasheet, PDF (15/24 Pages) Texas Instruments – DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz

ity is zero or negative, the data shall be sent unmodified. If the
running word disparity is negative and the current data dis-
parity is positive, the data shall be sent unmodified. If the
running word disparity is negative and the current data dis-
parity is zero or negative, the data shall be sent inverted. If
the running word disparity is zero, the data shall be sent in-
verted.
DC Balance mode is set when the BAL pin on the transmitter
is tied HIGH - see pin descriptions. DC Balancing is useful on
long cable applications which are typically greater than 5 me-
ters in length.
3. Deskew
Deskew is supported in the DC Balance mode only (BAL =
high on DS90CR483A). The “DESKEW” pin on the receiver
when set high will deskew a minimum of ±1 LVDS data bit
time skew from the ideal strobe location between signals ar-
riving on independent differential pairs (pair-to-pair skew). It
is required that the “DS_OPT” pin on the Transmitter must be
applied low for a minimum of four clock cycles to complete the
deskew operation. It is also required that this must be per-
formed at least once at any time after the PLLs have locked
to the input clock frequency. If power is lost, or if the cable has
been switched, this procedure must be repeated or else the
receiver may not sample the incoming LVDS data correctly.
When the receiver is in the deskew mode, all receiver data
outputs are set to a LOW state, but the receiver clock output
is still active and switching. Setting the “DESKEW” pin to low
will disable the deskew operation and allow the receiver to
operation on a fixed data sampling strobe. In this case, the
”DS_OPT” pin on the transmitter must then be set high.
The DS_OPT pin at the input of the transmitter
(DS90CR483A) is used to initiate the deskew calibration pat-
tern. It must be applied low for a minimum of four clock cycles
in order for the receiver to complete the deskew operation.
For this reason, the LVDS clock signal with DS_OPT applied
high (active data sampling) shall be 1111000 or 1110000 pat-
tern. During the deskew operation with DS_OPT applied low,
the LVDS clock signal shall be 1111100 or 1100000 pattern.
The transmitter will also output a series of 1111000 or
1110000 onto the LVDS data lines (TxOUT 0-7) during
deskew so that the receiver can automatically calibrated the
data sampling strobes at the receiver inputs. Each data chan-
nel is deskewed independently and is tuned with a step size
of 1/3 of a bit time over a range of +/−1 TBIT from the ideal
strobe location. The Deskew feature operates up to clock
rates of 80 MHz only. If the Receiver is enabled in the deskew
mode, then it must be trained before data transfer.
CLOCK JITTER
The transmitter is designed to reject cycle-to-cycle jitter which
may be seen at the transmitter input clock. Very low cycle-to-
cycle jitter is passed on to the transmitter outputs. Cycle-to-
cycle jitter has been measured over frequency to be less than
100 ps with input step function jitter applied. This should be
subtracted from the RSKM/RSKMD budget as shown and de-
scribed in and . This rejection capability significantly reduces
the impact of jitter at the TXinput clock pin, and improves the
accuracy of data sampling in the receiver. Transmitter output
jitter is effected by PLLVCC noise and input clock jitter - min-
imize supply noise and use a low jitter clock source to limit
output jitter. The falling edge of the input clock to the trans-
mitter is the critical edge and is used by the PLL circuit.
RSKM - RECEIVER SKEW MARGIN
RSKM is a chipset parameter and is explained in AN-1059 in
detail. It is the difference between the transmitter’s pulse po-
sition and the receiver’s strobe window. RSKM must be
greater than the summation of: Interconnect skew, LVDS
Source Clock Jitter (TJCC), and ISI (if any). See . Interconnect
skew includes PCB traces differences, connector skew and
cable skew for a cable application. PCB trace and connector
skew can be compensated for in the design of the system.
Cable skew is media type and length dependant.
RSKMD - RECEIVER SKEW MARGIN WITH DESKEW
RSKMD is a chipset parameter and is applicable when the
DESKEW feature of the DS90CR484A is employed. It is the
difference between the receiver’s strobe window and the ideal
pulse locations. The DESKEW feature adjusts for skew be-
tween each data channel and the clock channel. This feature
is supported up to 80 MHz clock rate. RSKMD must be greater
than the summation of: Transmitter’s Pulse Position variance,
LVDS Source Clock Jitter (TJCC), and ISI (if any). See . With
Deskew, RSKMD is ≥ 25% of TBIT. Deskew compensates for
interconnect skew which includes PCB traces differences,
connector skew and cable skew (for a cable application). PCB
trace and connector skew can be compensated for in the de-
sign of the system. Note, cable skew is media type and length
dependant. Cable length may be limited by the RSKMD pa-
rameter prior to the interconnect skew reaching 1 TBIT in
length due to ISI effects.
POWER DOWN
Both transmitter and receiver provide a power down feature.
When asserted current draw through the supply pins is mini-
mized and the PLLs are shut down. The transmitter outputs
are in TRI-STATE when in power down mode. The receiver
outputs are forced to a active LOW state when in the power
down mode. (See Pin Description Tables). The PD pin should
be driven HIGH to enable the device once V_CC is stable.
CONFIGURATIONS
The transmitter is designed to be connected typically to a sin-
gle receiver load. This is known as a point-to-point configu-
ration. It is also possible to drive multiple receiver loads if
certain restrictions are made. Only the final receiver at the end
of the interconnect should provide termination across the pair.
In this case, the driver still sees the intended DC load of 100
Ohms. Receivers connected to the cable between the trans-
mitter and the final receiver must not load down the signal. To
meet this system requirement, stub lengths from the line to
the receiver inputs must be kept very short.
CABLE TERMINATION
A termination resistor is required for proper operation to be
obtained. The termination resistor should be equal to the dif-
ferential impedance of the media being driven. This should be
in the range of 90 to 132 Ohms. 100 Ohms is a typical value
common used with standard 100 Ohm twisted pair cables.
This resistor is required for control of reflections and also to
complete the current loop. It should be placed as close to the
receiver inputs to minimize the stub length from the resistor
to the receiver input pins.
HOW TO CONFIGURE FOR BACKPLANE APPLICATIONS
In a backplane application with differential line impedance of
100Ω the differential line pair-to-pair skew can controlled by
trace layout. The transmitter-DS90CR483A “DS_OPT” pin
may be set high. In a backplane application with short PCB
distance traces, pre-emphasis from the transmitter is typically
not required. The “PRE” pin should be left open (do not tie to
ground). A resistor pad provision for a pull up resistor to Vcc
15
www.national.com