LP3910SQ-AN Datasheet, PDF (48/60 Pages) National Semiconductor (TI) – Power Management IC for Hard Drive Based Portable Media Players

BUCK1, BUCK2: Synchronous Step Down Magnetic DC/DC Converters
FUNCTIONAL DESCRIPTION
The LP3910SQ-AN, incorporates two high efficiency syn-
chronous switching BUCK regulators, BUCK1 and BUCK2
that deliver a constant voltage from a wall adapter or a single
Li-Ion battery to the portable system processors, Memory and
I/O. Using a voltage mode architecture with synchronous rec-
tification, both bucks have the ability to deliver up to 600 mA
depending on the input voltage and output voltage (voltage
head room), and the inductor chosen (maximum current ca-
pability).
and associated power loss. Synchronous rectification pro-
vides a significant improvement in efficiency whenever the
output voltage is relatively low compared to the voltage drop
across an ordinary rectifier diode.
CURRENT LIMITING
A current limit feature allows the buck to protect itself and ex-
ternal components during overload conditions PWM mode
implements cycle-by-cycle current limiting using an internal
comparator that trips at 1000 mA (typical).
There are three modes of operation depending on the current
required—PWM, PFM, and shutdown. PWM mode handles
current loads of approximately 70 mA or higher, delivering
voltage precision of ±3% with 90% efficiency or better. Lighter
output current loads cause the device to automatically switch
into PFM for reduced current consumption (I_Q = 15 µA typ.)
and a longer battery life. The Standby operating mode turns
off the device, offering the lowest current consumption. PWM
or PFM mode is selected automatically or PWM mode can be
forced through the setting of the buck control register.
Both BUCK1 and BUCK2 can operate up to a 100% duty cycle
(PMOS switch always on). Additional features include soft-
start, under-voltage lock-out, current overload protection, and
thermal overload protection.
PFM OPERATION
At very light loads, the converter enters PFM mode and op-
erates with reduced switching frequency and supply current
to maintain high efficiency.
The part will automatically transition into PFM mode when ei-
ther of two conditions occurs for a duration of 32 or more clock
cycles:
The inductor current becomes discontinuous orThe peak
PMOS switch current drops below the I_MODE level
CIRCUIT OPERATION DESCRIPTION
A buck converter contains a control block, a switching PFET
connected between input and output, a synchronous rectify-
ing NFET connected between the output and ground (BCK-
GND pin) and a feedback path. During the first portion of each
switching cycle, the control block turns on the internal PFET
switch. This allows current to flow from the input through the
inductor to the output filter capacitor and load. The inductor
limits the current to a ramp with a slope of V_IN-V_OUT/L.
During PFM operation, the converter positions the output volt-
age slightly higher than the nominal output voltage during
PWM operation, allowing additional headroom for voltage
drop during a load transient from light to heavy load. The PFM
comparators sense the output voltage via the feedback pin
and control the switching of the output FETs such that the
output voltage ramps between 0.8% and 1.6% (typical) above
the nominal PWM output voltage. If the output voltage is be-
low the ‘high’ PFM comparator threshold, the PMOS power
switch is turned on. It remains on until the output voltage ex-
ceeds the ‘high’ PFM threshold or the peak current exceeds
the I_PFM level set for PFM mode. The typical peak current in
PFM mode is:
by storing energy in a magnetic field. During the second por-
tion of each cycle, the control block turns the PFET switch off,
blocking current flow from the input, and then turns the NFET
synchronous rectifier on. The inductor draws current from
ground through the NFET to the output filter capacitor and
load, which ramps the inductor current down with a slope of
The output filter stores charge when the inductor current is
high, and releases it when low, smoothing the voltage across
the load.
PWM OPERATION
During PWM operation the converter operates as a voltage-
mode controller with input voltage feed forward. This allows
the converter to achieve excellent load and line regulation.
The DC gain of the power stage is proportional to the input
voltage. To eliminate this dependence, feed forward voltage
inversely proportional to the input voltage is introduced.
INTERNAL SYNCHRONOUS RECTIFICATION
While in PWM mode, the buck uses an internal NFET as a
synchronous rectifier to reduce rectifier forward voltage drop
Once the PMOS power switch is turned off, the NMOS power
switch is turned on until the inductor current ramps to zero.
When the NMOS zero-current condition is detected, the
NMOS power switch is turned off. If the output voltage is be-
low the ‘high’ PFM comparator threshold (see figure 4), the
PMOS switch is again turned on and the cycle is repeated
until the output reaches the desired level. Once the output
reaches the ‘high’ PFM threshold, the NMOS switch is turned
on briefly to ramp the inductor current to zero and then both
output switches are turned off and the part enters an ex-
tremely low power mode. Quiescent supply current during this
‘sleep’ mode is less than 30 µA, which allows the part to
achieve high efficiencies under extremely light load condi-
tions. When the output drops below the ‘low’ PFM threshold,
the cycle repeats to restore the output voltage to ≈1.6%
above the nominal PWM output voltage.
If the load current should increase during PFM mode (see
following figure) causing the output voltage to fall below the
‘low2’ PFM threshold, the part will automatically transition into
fixed-frequency PWM mode.
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