LP3910SQ-AN Datasheet, PDF (30/60 Pages) National Semiconductor (TI) – Power Management IC for Hard Drive Based Portable Media Players

PON Register (00)h Power On Event Register
Access
Data
D7–5
Read Only 0
Reserved
Reset n/a
D4
rw
PACK
0: Disable Power,
go in standby, and
wait for power on
event.
1: Acknowledge
Power On request
0
D3
Read Only
Battery Insert
0: default
1: Battery Insert
caused by Battery
Insertion
0
D2
PON by ONOFF
0: default
1: ONOFF caused
Power On event
0
D1
D0
PON by CHG_IN
0: default
PON by USB
Power
0: default
1: Power On caused 1: Power On caused
by CHG_IN power by USB power
detection
detection
0
0
External Power and Battery Detection
When a Wall Adapter is detected, regardless of the battery
voltage, the LP3910SQ-AN moves to the Active Mode and the
Power-up sequencer is started. Similar to the ONOFF pin,
there is a 32 ms deglitch time to ensure a clean wall adapter
detection and the system processor needs to set the PACK
bit (D4) in the PON register or the POWERACK pin within 128
ms (max) of the start of the power-up sequencer.
When USB PWR is detected and the battery is above the low
battery alarm threshold, the LP3910SQ-AN moves to the Ac-
tive Mode and the Power-up sequencer is started. Similar to
the ONOFF pin, there is a 32 ms deglitch time to ensure a
clean USB detection and the system processor needs to set
the PACK bit (D4) in the PON register or the POWERACK pin
within 128 ms (max) of the start of the power-up sequencer.
If the battery is below the low battery alarm threshold, the
system will remain powered down until the USBPWR charges
the battery up to the battery low alarm threshold, at which
point the power-up sequencer is started.
The four LSB bits of the PON register indicate which PON
source was responsible for moving the LP3910SQ-AN out of
standby and into active mode:
Battery insert
ONOFF push button
CHG_IN detect (connection of power adapter)
USB power (plug-in of powered USB cable)
These bits are cleared upon powering off.
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