LP3910SQ-AN Datasheet, PDF (28/60 Pages) National Semiconductor (TI) – Power Management IC for Hard Drive Based Portable Media Players

BATTLOW Register (04)h Battery Low Alarm Register
Access
Data
Reset
D7–5
Read Only 0
reserved
n/a
D4–0
rw
Battery Low threshold voltage (V)
5’h14–1F
2.50
5’h13
2.55
5’h12
2.60
5’h11
2.65
5’h10
2.70
5’h0F
2.75
5’h0E
2.80
5’h0D
2.85
5’h0C
2.90
5’h0B
2.95
5’h0A
3.00
5’h09
3.05
5’h08
3.10
5’h07
3.15
5’h06
3.20
5’h05
3.25
5’h04
3.30
5’h03
3.35
5’h02
3.40
5’h01
3.45
5’h00
3.50
5’h0C
2.90
Battery low IRQ threshold Voltage (V)
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.65
3.70
3.10
PowerOff Mode
In Power Off mode the main battery, the battery charger sup-
ply, and the USB supply are below their minimum on levels.
All internal circuits are disabled as the supply voltage is below
the level to activate them. The LP3910SQ-AN is in Power Off
mode when the battery voltage is below the battery V_UVLO
(2.4V typ) except when a valid external supply is detected.
Standby
When the LP3910SQ-AN is in Standby Mode, the chip is
waiting for a valid power-on event to transition to Active Mode.
There are 3 valid wakeup signals. First is the ONOFF pin.
Second is Wall Adapter Insertion. Third is the USB insertion.
V_BATT must be greater than the battery V_UVLO in order to stay
in Standby Mode, otherwise the chip transitions to Power Off
Mode. Standby Mode is skipped when advancing from Power
Off Mode when a battery is inserted that is above the battery
low alarm threshold.
If the battery is below the battery low alarm threshold, Power
Off Mode transitions to Standby Mode. However, hot insertion
of the battery with the adapter connected is NOT permitted.
In Standby Mode, the current consumption is reduced to I_Q
(10 µA TYP).
Active Mode
All LP3910SQ-AN circuits are fully operational in Active
mode.
own delay after which it is enabled following a power-on event
or disabled following a power-off event. Following the
deglitching of the power-on event, the system bandgaps are
enabled. Following this is a 5 ms delay that internal circuitry
requires to cleanly powerup. The programmable delays are
measured from this time point. Following the deglitching of a
power-down event (up to 5 ms if POWERACK pin is used),
the power-down sequencer will start. Each delay ranges from
0 ms to 63 ms in steps of 1 ms and is factory programmed to
the desired values submitted by the system designer. As il-
lustrated below, the power-on/off sequencing is designed
around a 6-bit up/down timer that is clocked at 1 kHz. A pow-
er-on or power-off event will trigger the timer, which counts
up from 0 during a power-on sequence and counts down from
5'b11111 during a power-down cycle. The timer output is con-
nected to 5 comparators with factory programmed timeout
values that correspond to the on and off delays for each DC/
DC converter and the NRST pin. Once the timer has incre-
mented beyond the comparator timeout value during a power-
on cycle, the output of the comparator enables the corre-
sponding DC/DC converter or raises the NRST pin to a logic
high level. Subsequently, once the timer has decremented
below the comparator timeout value during a power-down cy-
cle, the output of the comparator will disable the correspond-
ing DC/DC converter or will activate the NRST pin to a logic
low level.
Power On/Off Sequencing
Each DC/DC converter (BUCK1, BUCK2, BUCK-Boost,
LDO1, LDO2) and the NRST pin of the LP3910SQ-AN has its
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