LP3910SQ-AN Datasheet, PDF (27/60 Pages) National Semiconductor (TI) – Power Management IC for Hard Drive Based Portable Media Players

Power State Table
LDO1,2
BUCK1,2
BUCK/BOOST
CHARGER
A/D Converter
NRST
I²C interface
Internal System Oscillator
Battery Monitor
Current consumption
Power Off
Off
Off
Off
Off
Off
Low
Off
Off
Off
<1 µA
Standby
Off
Off
Off
Off
Off
Low
Off
Off
On
10 µA (typ)
Active
On
On
On
On if Charger / USB Present
On
High
On
On
On
See Electrical Characteristics
Charger Standby
Off
Off
Off
On if Charger / USB Present
Off
Low
On
On
On
See Electrical Characteristics
Power-On-Reset
The LP3910SQ-AN is equipped with an internal Power-On-
Reset (“POR”) circuit that will reset the logic when V_DD <
V_POR. This guarantees that the logic is properly initialized
when V_DD rises above the minimum operating voltage of the
Logic and the internal oscillator that clocks the Sequential
Logic in the Control section.
Thermal Shutdown and Thermal Alarm
An internal temperature sensor monitors the junction temper-
ature of the LP3910SQ-AN and forcibly invokes standby
mode in the unusual case when the junction temperature of
the silicon exceeds the normal operating level due to exces-
sive loads on all power regulators and the Li-ion charger and/
or due to an abnormally high ambient temperature. The ther-
mal Shutdown threshold is 160°C.
The thermal shutdown is preceded by a Thermal alarm that
generates an interrupt request if unmasked (see Interrupt Re-
quest generation). The temperature threshold for triggering
the alarm is 115°C.
NRST Pin
The NRST pin is an open-drain output and is active low during
Standby, Power Off and Charger Standby modes. The NRST
timing is determined by a factory programmable counter.
Control Registers
The LP3910SQ-AN contains 14 user programmable registers
that configure the functionality of the individual modules in-
side the IC. Registers are programmed through an I²C inter-
face and have default values that are invoked during an
internal reset. Some of the default values can be tailored to
the specific needs of the system designer (see Application
Notes).
Throughout this product specification, the register address is
noted in hexadecimal notation immediately following the reg-
ister name as illustrated below:
PON Register (00)h Power On Event Register
D7–4
D3
D2
D1
D0
Battery Monitor
The battery voltage is monitored and will invoke the Power
Off mode when the battery low threshold is breached for more
than 5 ms (Typ.). The battery low threshold DEFAULT is fac-
tory programmed. The battery low threshold range is 2.5V–
3.5V with steps of 50 mV. The Battery low threshold in the
table below refers to a decreasing battery voltage. The thresh-
old when the battery voltage is transitioning out of the
V_BATTLOW is 50 mV (Typ.) higher than the values listed in the
table below due to a built-in hysteresis of 50 mV (Typ.).
The battery low IRQ is triggered 200 mV above the battery
low alarm threshold that powers down the IC. This gives the
user time for a controlled shutdown.
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