LP3910SQ-AN Datasheet, PDF (34/60 Pages) National Semiconductor (TI) – Power Management IC for Hard Drive Based Portable Media Players

I²C COMPATIBLE SERIAL INTERFACE
I²C Signals
The LP3910SQ-AN features an I²C compatible serial inter-
face, using two dedicated pins: I²C_SCL and I²C_SDA for
I²C clock and data respectively. Both signals need a pull-up
resistor according to the I²C specification. The LP3910SQ-AN
interface is an I²C slave that is clocked by the incoming SCL
clock.
Signal timing specifications are according to the I²C bus spec-
ification. The maximum bit rate is 400 kbit/s. See I²C specifi-
cation from Philips for further details.
I²C Data Validity
The data on I²C_SDA line must be stable during the HIGH
period of the clock signal (I²C_SCL), e.g., the state of the data
line can only be changed when CLK is LOW.
I²C Signals: Data Validity
I²C START and STOP Conditions
START and STOP bits classify the beginning and the end of
the I²C session. The START condition is defined the as the
I²C_SDA signal transitioning from HIGH to LOW while SCL
line is HIGH. The STOP condition is defined as the SDA tran-
sitioning from LOW to HIGH while I²C_SCL is HIGH. The I²C
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master always generates START and STOP bits. The I²C bus
is considered to be busy after a START condition and free
after a STOP condition. During data transmission, I²C master
can generate repeated START conditions. First START and
repeated START conditions are equivalent, function-wise.
START and STOP Conditions
Transferring Data
Every byte put on the I²C_SDA line must be eight bits long,
with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit.
The acknowledged related clock pulse is generated by the
master. The transmitter releases the I²C_SDA line (HIGH)
during the acknowledge clock pulse. The receiver must pull
down the I²C_SDA line during the 9th clock pulse, signifying
acknowledgement. A receiver which has been addressed
must generate an acknowledgement (“ACK”) after each byte
has been received.
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Register Write Cycle
After the START condition, the I²C master sends a chip ad-
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). For the eighth bit, a “0”
indicates a WRITE and a “1” indicates a READ. The second
byte selects the register to which the data will be written. The
third byte contains data that will be written to the selected
register.
LP3910SQ-AN has a chip address of 60’h, which is set by a
metal mask option.
I²C Chip Address
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30101211
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