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| LM3743_08 Datasheet, PDF (4/28 Pages) National Semiconductor (TI) – High-Performance Synchronous Buck Controller with Comprehensive Fault Protection Features | |||
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Symbol
Parameter
VRAMP PWM Ramp Amplitude
LOGIC INPUTS AND OUTPUTS
VCOMP/EN-HI COMP/EN pin logic high trip-point
VCOMP/EN-LO COMP/EN pin logic low trip-point
HICCUP MODE
NLSCYCLES Low-side sensing cycles before hiccup
mode
NLSRESET Low-side sensing cycles reset without
activating current limit
VUVP
Under Voltage Protection comparator
threshold
tGLICH-UVP Under Voltage Protection fault time before
hiccup mode
tHICCUP Hiccup timeout
tSS
Soft-start time coming out of hiccup mode
THERMAL RESISTANCE
θJA
Junction to Ambient Thermal Resistance
Conditions
Min Typ Max Units
1.0
V
0.65 0.9
V
0.1 0.45
V
15
Cycles
32
Cycles
400
mV
7
µs
5.5
ms
3.6
ms
235
°C/W
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device
operates correctly. Operating Ratings do not imply guaranteed performance limits.
Note 2: Practical lower limit of VCC depends on selection of the external MOSFET. See the MOSFET GATE DRIVERS section under Application Information for
further details.
Note 3: ESD using the human body model which is a 100 pF capacitor discharged through a 1.5 k⦠resistor into each pin. Test method is per JESD22âA114.
www.national.com
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