LM3743_08 Datasheet, PDF (2/28 Pages) National Semiconductor (TI) – High-Performance Synchronous Buck Controller with Comprehensive Fault Protection Features

Connection Diagram
20177402
10-Lead Plastic MSOP
NS Package Number MUB10A
Top View
Ordering Information
Order Number
LM3743MM-300
LM3743MMX-300
LM3743MM-1000
LM3743MMX-1000
Frequency Option
300 kHz
300 kHz
1 MHz
1 MHz
Top Mark
SKPB
SKPB
SKNB
SKNB
Pin Descriptions
VCC (Pin 1) Supply rail for the controller section of the IC. A
minimum capacitance of 1 µF, preferably a multi-layer ce-
ramic capacitor type (MLCC), must be connected as close as
possible to the V_CC and GND pin and a 1 to 4.99Ω resistance
must be connected in series from the supply rail to the Vcc
pin. See VCC FILTERING in the Design Consideration sec-
tion for further details.
LGATE (Pin 2) Gate drive for the low-side N-channel MOS-
FET. This signal is interlocked with HGATE to avoid a shoot-
through problem.
GND (Pin 3) Power ground (PGND) and signal ground
(SGND). Connect the bottom feedback resistor between this
pin and the feedback pin.
ILIM (Pin 4) Low side current limit threshold setting pin. This
pin sources a fixed 50 µA current. A resistor of appropriate
value should be connected between this pin and the drain of
the low-side N-FET.
FB (Pin 5) Feedback pin. This is the inverting input of the error
amplifier used for sensing the output voltage and compen-
sating the control loop.
COMP/EN (Pin 6) Output of the error amplifier and enable
pin. The voltage level on this pin is compared with an internally
NSC Package Drawing
MUB10A
MUB10A
MUB10A
MUB10A
Supplied As
1000 units in Tape and Reel
3500 units in Tape and Reel
1000 units in Tape and Reel
3500 units in Tape and Reel
generated ramp signal to determine the duty cycle. This pin
is necessary for compensating the control loop. Forcing this
pin to ground will shut down the IC.
SS/TRACK (Pin 7) Soft-start and tracking pin. This pin is
connected to the non-inverting input of the error amplifier dur-
ing initial soft-start, or any time the voltage is below the
reference. To track the rising ramp of another power supply's
output, connect a resistor divider from the output of that sup-
ply to this pin as described in Application Information.
SW (Pin 8) Switch pin. The lower rail of the high-side N-FET
driver. Also used for the high side current limit sensing.
HGATE (Pin 9) Gate drive for the high-side N-channel MOS-
FET. This signal is interlocked with LGATE to avoid a shoot-
through problem.
BOOT (Pin 10) Supply rail for the N-channel MOSFET high
gate drive. The voltage should be at least one gate threshold
above the regulator input voltage to properly turn on the high-
side N-FET. See MOSFET Gate Drivers in the Application
Information section for more details on how to select MOS-
FETs.
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