LM3743_08 Datasheet, PDF (19/28 Pages) National Semiconductor (TI) – High-Performance Synchronous Buck Controller with Comprehensive Fault Protection Features

Losses in the high-side MOSFET can be broken down into
conduction loss, gate charging loss, and switching loss. Con-
duction, or I²R loss, is approximately:
For the high side FET:
P_C = D (I_OUT2 x R_DSON-HI x 1.3)
For the low side FET:
P_C = (1 - D) x (I_OUT2 x R_DSON-LO x 1.3)
In the above equations the factor 1.3 accounts for the in-
crease in MOSFET R_DSON due to heating. Alternatively, the
1.3 can be ignored and the R_DSON of the MOSFET estimated
using the R_DSON vs. Temperature curves in the MOSFET
manufacturer datasheet.
Gate charging loss results from the current driving the gate
capacitance of the power MOSFETs, and is approximated as:
P_GC = (V_CC) x Q_G x f_SW
V_CC is the driving voltage (see MOSFET Gate Driver section)
and Q_G is the gate charge of the MOSFET. If multiple devices
will be placed in parallel, their gate charges can simply be
summed to form a cumulative Q_G.
Switching loss occurs during the brief transition period as the
high-side MOSFET turns on and off, during which both current
and voltage are present in the channel of the MOSFET. It can
be approximated as:
P_SW = 0.5 x V_IN x I_OUT x (t_r + t_f) x f_SW
where t_r and t_f are the rise and fall times of the MOSFET.
Switching loss occurs in the high-side MOSFET only.
For this example, the maximum drain-to-source voltage ap-
plied to either MOSFET is 5.5V. The maximum drive voltage
at the gate of the high-side MOSFET is 5.0V, and the maxi-
mum drive voltage for the low-side MOSFET is 5.5V. For
designs between 5A and 10A, single MOSFETs in SO-8 pro-
vide a good trade-off between size, cost, and efficiency.
V_CC Filtering
To ensure smooth DC voltage for the chip supply a 1 µF (C3),
X5R MLCC type or better must be placed as close as possible
to the V_CC and GND pin. Together with a small 1 to 4.99Ω
resistor placed between the input rail and the V_CC pin, a low
pass filter is formed to filter out high frequency noise from
injecting into the V_CC rail. Since V_CC is also the sense pin for
the high-side current limit, the resistor should connect close
to the drain of the high-side MOSFET to prevent IR drops due
to trace resistance. A second design consideration is the low
pass filter formed by C3 and R6 on the V_CC pin, a fast slew
rate, large amplitude load transient may cause a larger volt-
age droop on C_IN than on V_CC pin. This may lead to a lower
current at which high-side protection may occur. Thus in-
crease the bulk input capacitor if the high-side current limit is
engaging due to a dynamic load transient behavior as ex-
plained above.
Bootstrap Diode (D1)
The MBR0520 and BAT54 work well as a bootstrap diode in
most designs. Schottky diodes are the preferred choice for
the bootstrap circuit because of their low forward voltage
drop. For circuits that will operate at high ambient temperature
the Schottky diode datasheet must be read carefully to ensure
that the reverse current leakage at high temperature does not
increase enough to deplete the charge on the bootstrap ca-
pacitor while the high side FET is on. Some Schottky diodes
increase their reverse leakage by as much as 1000 times at
high temperatures. Fast rectifier and PN junction diodes
maintain low reverse leakage even at high ambient tempera-
ture. These diode types have higher forward voltage drop but
can still be used for high ambient temperature operation.
Control Loop Compensation
The LM3743 uses voltage-mode (‘VM’) PWM control to cor-
rect changes in output voltage due to line and load transients.
VM requires careful small signal compensation of the control
loop for achieving high bandwidth and good phase margin.
The control loop is comprised of two parts. The first is the
power stage, which consists of the duty cycle modulator, out-
put inductor, output capacitor, and load. The second part is
the error amplifier, which for the LM3743 is a 30 MHz op-amp
used in the classic inverting configuration. Figure 8 shows the
regulator and control loop components.
20177413
FIGURE 8. Power Stage and Error Amp
One popular method for selecting the compensation compo-
nents is to create Bode plots of gain and phase for the power
stage and error amplifier. Combined, they make the overall
bandwidth and phase margin of the regulator easy to see.
Software tools such as Excel, MathCAD, and Matlab are use-
ful for showing how changes in compensation or the power
stage affect system gain and phase.
The power stage modulator provides a DC gain A_DC that is
equal to the input voltage divided by the peak-to-peak value
of the PWM ramp. This ramp is 1.0V_pk-pk for the LM3743. The
inductor and output capacitor create a double pole at fre-
quency f_DP, and the capacitor ESR and capacitance create a
single zero at frequency f_ESR. For this example, with V_IN =
5.0V, these quantities are:
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