LM3743_08 Datasheet, PDF (22/28 Pages) National Semiconductor (TI) – High-Performance Synchronous Buck Controller with Comprehensive Fault Protection Features

The total control loop transfer function H is equal to the power
stage transfer function multiplied by the error amplifier trans-
fer function.
H = G_PS x H_EA
The bandwidth and phase margin can be read graphically
from Bode plots of H_EA as shown in Figure 11.
20177429
20177450
FIGURE 11. Overall Loop Gain and Phase
The bandwidth of this example circuit is 59 kHz, with a phase
margin of 60°.
EFFICIENCY CALCULATIONS
The following is a sample calculation.
A reasonable estimation of the efficiency of a switching buck
controller can be obtained by adding together the Output
Power (P_OUT) loss and the Total Power loss (P_LOSS):
FET Switching Loss (P_SW)
P_SW = P_SW(ON) + P_SW(OFF)
P_SW = 0.5 x V_IN x I_OUT x (t_r + t_f) x f_SW
P_SW = 0.5 x 5V x 10A x 300 kHz x 67 ns
P_SW = 503 mW
The Si4866DY has a typical turn-on rise time t_r and turn-off
fall time t_f of 32 ns and 35 ns, respectively. The switching
losses for the upper FET (Q1) is 0.503W. The low side FET
(Q2) does not incur switching losses.
FET Conduction Loss (P_CND)
P_CND = P_CND1 + P_CND2
P_CND1 = I^2OUT x R_DS(ON) x k x D
P_CND2 = I^2OUT x R_DS(ON) x k x (1-D)
R_DS(ON) = 4.5 mΩ and the k factor accounts for the increase
in R_DS(ON) due to heating. k = 1.3 at T_J = 100°C
P_CND1 = (10A)² x 4.5 mΩ x 1.3 x 0.36
P_CND2 = (10A)² x 4.5 mΩ x 1.3 x (1 - 0.36)
P_CND = P_CND1 + P_CND2
P_CND = 211 mW + 374 mW = 585 mW
FET Gate Charging Loss (P_GATE)
P_{GATE_H} = n x ( V_CC - V_D1 ) x Q_GS x f_SW
P_{GATE_L} = n x V_CC x Q_GS x f_SW
P_GATES = [ 1 x ( 5.0V - 0.4V ) x 22 nC x 300 kHz ] + [ 1 x ( 5.0V )
x 22 nC x 300 kHz ]
P_GATES = 29 mW + 33 mW = 62 mW
The value n is the total number of FETs used and Q_GS is the
typical gate-source charge value, which is 21 nC. For the
Si4866DY the gate charging loss is 62 mW.
Thus the total MOSFET losses are:
P_FET = P_SW + P_CND + P_GATES =
503 mW + 585 mW + 62 mW
P_FET = 1.15 W
There are few additional losses that are taken into account:
IC Loss (P_IC)
P_OP = I_{Q_VCC} x V_CC
P_DR = [[ (n x Q_GS x f_SW) / D] +[ (n x Q_GS x f_SW) / (1–D) ]] x V_CC
where P_OP is the operating loss, P_DR is the driver loss, I_Q-
VCC ^{is the typical operating V}CC ^current
P_OP= ( 1.3 mA x 5.0V )
P_DR= [( 1 x 22 nC x 300 kHz ) / .36 ] + [( 1 x 22 nC x 300
kHz ) / .64 ] x V_CC
P_IC= P_OP + P_DR
P_IC= 6.5 mW + 137 mW = 143.5 mW
Input Capacitor Loss (P_CAP)
The Output Power (P_OUT) for the Typical Application Circuit
design is (1.8V x 10A) = 18W. The Total Power (P_LOSS), with
an efficiency calculation to complement the design, is shown
below.
The majority of the power losses are due to the low side and
high side MOSFET’s losses. The losses in any MOSFET are
switching (P_SW), conduction losses (P_CND), and gate charging
losses (P_GATE)
where,
www.national.com
22