LM3743_08 Datasheet, PDF (23/28 Pages) National Semiconductor (TI) – High-Performance Synchronous Buck Controller with Comprehensive Fault Protection Features

Here n is the number of paralleled capacitors, ESR is the
equivalent series resistance of each, and P_CAP is the dissipa-
tion in each. So for example if we use only one input capacitor
of 10mΩ.
P_CAP = 230 mW
Output Inductor Loss (P_IND)
P_IND = I^2OUT x DCR
where DCR is the DC resistance. Therefore, for example
P_IND = (10A)² x 3 mΩ
P_IND = 302 mW
Total System Efficiency
P_LOSS = P_FET + P_IC + P_CAP + P_IND
PCB LAYOUT CONSIDERATIONS
To produce an optimal power solution with the LM3743, good
layout and design of the PCB are as important as component
selection. The following are several guidelines to aid in cre-
ating a good layout. For an extensive PCB layout explanation
refer to AN-1229.
Separate Power Ground and Signal Ground
Good layout techniques include a dedicated ground plane,
preferably on an internal layer. Signal level components like
the compensation and feedback resistors should be connect-
ed to a section of this internal plane, signal ground. The signal
ground section of the plane should be connected to the power
ground at a single point. The best place to connect the signal
ground and power ground is right at the GND pin of the IC.
Low Impedance Power Path
The power path includes the input capacitors, power FETs,
output inductor, and output capacitors. Keep these compo-
nents on the same side of the PCB and connect them with
thick traces or copper planes on the same layer. Vias add
resistance and inductance to the power path, and have high
impedance connections to internal planes than do top or bot-
tom layers of a PCB. If heavy switching currents must be
routed through vias and/or internal planes, use multiple vias
in parallel to reduce their resistance and inductance. The
power components must be kept close together. The longer
the paths that connect them, the more they act as antennas,
radiating unwanted EMI.
Minimize the Switch Node Copper
The plane that connects the power FETs and output inductor
together radiates more EMI as it gets larger. Use just enough
copper to give low impedance to the switching currents.
Kelvin Traces For Sense Lines
The drain and the source of the high-side FET should be con-
nected as close as possible to the V_CC filter resistor (R6) and
the SW pin and each pin should connect with a separate trace.
The feedback trace should connect the positive node of the
output capacitor and connect to the top feedback resistor
(R2). Keep this trace away from the switch node and from the
output inductor. If driving the COMP pin low with a signal BJT
or MOSFET make sure to keep the signal transistor as close
as possible to the pin and keep the trace away from EMI ra-
diating nodes and components.
23
www.national.com