LM3743_08 Datasheet, PDF (16/28 Pages) National Semiconductor (TI) – High-Performance Synchronous Buck Controller with Comprehensive Fault Protection Features

amount equal to the 'Miller plateau'. It can be shown that this
plateau is equal to the threshold voltage of the chosen MOS-
FET plus a small amount equal to I_OUT/g. Here I_OUT is the
maximum load current of the application, and g is the
transconductance of this MOSFET (typically about 100 for
logic-level devices). That means we must choose V_{BOOT_DC}
to at least exceed the Miller plateau level. This may therefore
affect the choice of the threshold voltage of the external MOS-
FETs, and that in turn may depend on the chosen V_IN rail.
So far in the discussion above, the forward drop across the
bootstrap diode has been ignored. But since that does affect
the output of the driver, it is a good idea to include this drop
in the following examples. Looking at the Typical Application
schematic, this means that the difference voltage V_IN - V_D1,
which is the voltage the bootstrap capacitor charges up to,
must always be greater than the maximum tolerance limit of
the threshold voltage of the upper MOSFET. Here V_D1 is the
forward voltage drop across the bootstrap diode D1. This
voltage drop may place restrictions on the type of MOSFET
selected.
The capacitor C10 serves to maintain enough voltage be-
tween the top MOSFET gate and source to control the device
even when the top MOSFET is on and its source has risen up
to the input voltage level. The charge pump circuitry is fed
from V_IN, which can operate over a range from 3.0V to 5.5V.
Using this basic method the voltage applied to the high side
gate V_IN - V_D1. This method works well when V_IN is 5V±10%,
because the gate drives will get at least 4.0V of drive voltage
during the worst case of V_IN-MIN = 4.5V and V_D1-MAX = 0.5V.
Logic level MOSFETs generally specify their on-resistance at
V_GS = 4.5V. When V_CC = 3.3V±10%, the gate drive at worst
case could go as low as 2.5V. Logic level MOSFETs are not
guaranteed to turn on, or may have much higher on-resis-
tance at 2.5V. Sub-logic level MOSFETs, usually specified at
V_GS = 2.5V, will work, but are more expensive and tend to
have higher on-resistance.
LOW-SIDE CURRENT LIMIT
The main current limit of the LM3743 is realized by sensing
the voltage drop across the low-side FET as the load current
passes through it. The R_DSON of the MOSFET is a known val-
ue; hence the voltage across the MOSFET can be determined
as:
V_DS = I_OUT x R_DSON
The current flowing through the low-side MOSFET while it is
on is the falling portion of the inductor current. The current
limit threshold is determined by an external resistor, R1, con-
nected between the switching node and the ILIM pin. A con-
stant current (I_ILIM) of 50 µA typical is forced through R1,
causing a fixed voltage drop. This fixed voltage is compared
against V_DS and if the latter is higher, the current limit of the
chip has been reached. To obtain a more accurate value for
R1 you must consider the operating values of R_DSON and
I_ILIM at their operating temperatures in your application and
the effect of slight parameter variations from part to part. R1
can be found by using the following equation using the
R_DSON value of the low side MOSFET at it's expected hot
temperature and the absolute minimum value expected over
the full temperature range for the I_ILIM which is 42.5 µA:
R1 = R_DSON-HOT x I_CLIM / I_ILIM
For example, a conservative 15A current limit (I_CLIM) in a 10A
design with a R_DSON-HOT of 10 mΩ would require a 3.83 kΩ
resistor. The LM3743 enters current limit mode if the inductor
current exceeds the set current limit threshold. The inductor
current is first sampled 50 ns after the low-side MOSFET turns
on. Note that in normal operation mode the high-side MOS-
FET always turns on at the beginning of a clock cycle. In
current limit mode, by contrast, the high-side MOSFET on-
pulse is skipped. This causes inductor current to fall. Unlike
a normal operation switching cycle, however, in a current limit
mode switching cycle the high-side MOSFET will turn on as
soon as inductor current has fallen to the current limit thresh-
old.
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FIGURE 5. Current Limit Threshold
The low-side current sensing scheme can only limit the cur-
rent during the converter off-time, when inductor current is
falling. Therefore in a typical current limit plot the valleys are
normally well defined, but the peaks are variable, according
to the duty cycle, see Figure 5. The PWM error amplifier and
comparator control the pulse of the high-side MOSFET, even
during current limit mode, meaning that peak inductor current
can exceed the current limit threshold. For example, during
an output short-circuit to ground, and assuming that the out-
put inductor does not saturate, the maximum peak inductor
current during current limit mode can be calculated with the
following equation:
Where T_SW is the inverse of switching frequency f_SW. The 200
ns term represents the minimum off-time of the duty cycle,
which ensures enough time for correct operation of the cur-
rent sensing circuitry.
In order to minimize the temperature effects of the peak in-
ductor currents, the IC enters hiccup mode after 15 over
current events, or a long current limit event that lasts 15
switching cycles (the counter is reset when 32 non-current
limit cycles occur in between two current limit events). Hiccup
mode will be discussed in further detail in the “Hiccup Mode
and Internal Soft-Start” section.
HIGH-SIDE COARSE CURRENT LIMIT
The LM3743 employs a comparator to monitor the voltage
across the high-side MOSFET when it is on. This provides
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