LM3743_08 Datasheet, PDF (15/28 Pages) National Semiconductor (TI) – High-Performance Synchronous Buck Controller with Comprehensive Fault Protection Features

two supplies identical soft-start times would be 205Ω. A timing
diagram for the equal soft-start time case is shown in Figure
2.
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FIGURE 2. Tracking with Equal Soft-Start Time
TRACKING WITH EQUAL SLEW RATES
The tracking feature can alternatively be used not to make
both rails reach regulation at the same time but rather to have
similar rise rates (in terms of output dV/dt). In this case, the
tracking resistors can be determined based on the following
equation:
For the example case of V_OUT1 = 5V and V_OUT2 = 1.8V, with
R_T2 set to 1 kΩ as before, R_T1 is calculated from the above
equation to be 887Ω. A timing diagram for the case of equal
slew rates is shown in Figure 3.
drivers must be shut-off before the master powers down. This
is achieved by shutting down the LM3743 or bring V_CC below
UVLO falling threshold. In this case the load will not be dis-
charged.
SHUTDOWN
The LM3743 IC can be put into shutdown mode by bringing
the voltage at the COMP/EN pin below 0.45V (typ). The qui-
escent current during shutdown is approximately 6 µA (typ).
During shutdown both the high-side and low-side FETs are
disabled. The soft-start capacitor is discharged through an
internal FET so that the output voltage rises in a controlled
fashion when the part is enabled again. When enabled a 4 µA
pull-up current increases the charge of the compensation ca-
pacitors.
UNDER VOLTAGE LOCK-OUT (UVLO)
If V_CC drops below 2.66V (typ), the chip enters UVLO mode.
UVLO consists of turning off the top and bottom FETs and
remaining in that condition until V_CC rises above 2.84V (typ).
As with shutdown, the soft-start capacitor is discharged
through an internal FET, ensuring that the next start-up will
be controlled by the soft-start circuitry.
MOSFET GATE DRIVE
The LM3743 has two gate drivers designed for driving N-
channel MOSFETs in synchronous mode. Power for the high
gate driver is supplied through the BOOT pin, while driving
power for the low gate is provided through the V_CC pin. The
BOOT voltage is supplied from a local charge pump structure
which consists of a Schottky diode and 0.1 µF capacitor,
shown in Figure 4. Since the bootstrap capacitor (C10) is
connected to the SW node, the peak voltage impressed on
the BOOT pin is the sum of the input voltage (V_IN) plus the
voltage across the bootstrap capacitor (ignoring any forward
drop across the bootstrap diode). The bootstrap capacitor is
charged up by V_IN (called V_{BOOT_DC} here) whenever the upper
MOSFET turns off.
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FIGURE 3. Tracking with Equal Slew Rate
TRACKING AND SHUTDOWN SEQUENCING
LM3743 is designed to track the output of a master power
supply during start-up, but when the master supply powers
down the output capacitor of the LM3743 will discharge cycle
by cycle through the low-side FET. The off-time will reach
100% when the voltage at the track pin reaches zero volts.
This condition will persist as long as the master output voltage
is zero volts and the drivers of the LM3743 are still on. For
example if the load is required to not be discharged, the
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FIGURE 4. Charge Pump Circuit and Driver Circuitry
The output of the low-side driver swings between V_CC and
ground, whereas the output of the high-side driver swings be-
tween V_IN + V_{BOOT_DC} and V_IN. To keep the high-side MOS-
FET fully on, the Gate pin voltage of the MOSFET must be
higher than its instantaneous Source pin voltage by an
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