LM3743_08 Datasheet, PDF(20/28 Page) National Semiconductor (TI) – High-Performance Synchronous Buck Controller with Comprehensive Fault Protection Features

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LM3743_08 Datasheet, PDF (20/28 Pages) National Semiconductor (TI) – High-Performance Synchronous Buck Controller with Comprehensive Fault Protection Features

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In the equation for fDP, the variable RL is the power stage re-

sistance, and represents the inductor DCR plus the on resis-

tance of the top power MOSFET. RO is the output voltage

divided by output current. The power stage transfer function

GPS is given by the following equation, and Figure 9 shows

Bode plots of the phase and gain in this example.

a = LCO(RO + RC)

b = L + CO(RORL + RORC + RCRL)

c = RO + RL

bandwidth.) In practice, the loop could easily become unsta-

ble due to tolerances in the output inductor, capacitor, or

changes in output current, or input voltage. Therefore, the

loop is compensated using the error amplifier and a few pas-

sive components.

For this example, a Type III, or three-pole-two-zero approach

gives optimal bandwidth and phase.

In most voltage mode compensation schemes, including

Type III, a single pole is placed at the origin to boost DC gain

as high as possible. Two zeroes fZ1 and fZ2 are placed at the

double pole frequency to cancel the double pole phase lag.

Then, a pole, fP1 is placed at the frequency of the ESR zero.

A final pole fP2 is placed at one-half of the switching frequency.

The gain of the error amplifier transfer function is selected to

give the best bandwidth possible without violating the Nyquist

stability criteria. In practice, a good crossover point is one-fifth

of the switching frequency, or 60 kHz for this example. The

generic equation for the error amplifier transfer function is:

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In this equation the variable AEA is a ratio of the values of the

capacitance and resistance of the compensation compo-

nents, arranged as shown in Figure 8. AEA is selected to

provide the desired bandwidth. A starting value of 80,000 for

AEA should give a conservative bandwidth. Increasing the

value will increase the bandwidth, but will also decrease

phase margin. Designs with 45-60Â° are usually best because

they represent a good trade-off between bandwidth and

phase margin. In general, phase margin is lowest and gain

highest (worst-case) for maximum input voltage and minimum

output current. One method to select AEA is to use an iterative

process beginning with these worst-case conditions.

1. Increase AEA

2. Check overall bandwidth and phase margin

3. Change VIN to minimum and recheck overall bandwidth

and phase margin

4. Change IO to maximum and recheck overall bandwidth

and phase margin

The process ends when both bandwidth and phase margin

are sufficiently high. For this example input voltage can vary

from 4.5V to 5.5V and output current can vary from 0 to 10A,

and after a few iterations a moderate gain factor of 90 dB is

used.

The error amplifier of the LM3743 has a unity-gain bandwidth

of 30 MHz. In order to model the effect of this limitation, the

open-loop gain can be calculated as:

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FIGURE 9. Power Stage Gain and Phase

The double pole at 6 kHz causes the phase to drop to ap-

proximately -140Â° at around 15 kHz. The ESR zero, at 33.9

kHz, provides a +90Â° boost that prevents the phase from

dropping to -180Âº. If this loop were left uncompensated, the

bandwidth would be approximately 15 kHz and the phase

margin 40Â°. In theory, the loop would be stable, but would

suffer from poor DC regulation (due to the low DC gain) and

would be slow to respond to load transients (due to the low

The new error amplifier transfer function that takes into ac-

count unity-gain bandwidth is:

www.national.com

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