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COP87LXXCJ Datasheet, PDF (20/28 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 4k or 32k Memory and Comparator
Instruction Set (Continued)
INSTRUCTION SET
ADD
ADC
add
add with carry
SUBC
subtract with carry
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
X
LD A
LD mem
LD Reg
X
X
LD A
LD A
LD M
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Set bit
Reset bit
If bit
Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.
Exchange A with memory [B]
Exchange A with memory [X]
Load A with memory [B]
Load A with memory [X]
Load Memory Immediate
Clear A
Increment A
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
Swap nibbles of A
Set C
Reset C
If C
If not C
Jump absolute long
Jump absolute
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
Return from subroutine
Return and Skip
Return from Interrupt
Generate an interrupt
No operation
A ← A + MemI
A ← A + MemI + C, C ← Carry
HC ← Half Carry
A ← A + MemI +C, C ← Carry
HC ← Half Carry
A ← A and MemI
A ← A or MemI
A ← A xor MemI
Compare A and MemI, Do next if A = MemI
Compare A and MemI, Do next if A > MemI
Do next if lower 4 bits of B ≠ Imm
Reg ← Reg − 1, skip if Reg goes to 0
1 to bit, Mem (bit= 0 to 7 immediate)
0 to bit, Mem
If bit, Mem is true, do next instr.
A ↔ Mem
A ← MemI
Mem ← Imm
Reg ← Imm
A ↔ [B] (B ← B±1)
A ↔ [X] (X ← X±1)
A ← [B] (B ← B±1)
A ← [X] (X ← X±1)
[B] ← Imm (B ← B±1)
A←0
A←A+1
A←A−1
A ← ROM(PU,A)
A ← BCD correction (follows ADC, SUBC)
C → A7 → … → A0 → C
A7 … A4 ↔ A3 … A0
C ← 1, HC ← 1
C ← 0, HC ← 0
If C is true, do next instruction
If C is not true, do next instruction
PC ← ii (ii = 15 bits, 0 to 32k)
PC11..0 ← i (i = 12 bits)
PC ← PC + r (r is −31 to +32, not 1)
[SP] ← PL,[SP-1] ← PU,SP-2,PC ← ii
[SP] ← PL,[SP-1] ← PU,SP-2,PC11.. 0 ← i
PL ← ROM(PU,A)
SP+2,PL ← [SP],PU ← [SP-1]
SP+2,PL ← [SP],PU ← [SP-1],Skip next instruction
SP+2,PL ← [SP],PU ← [SP-1],GIE ← 1
[SP] ← PL,[SP−1] ← PU,SP-2,PC ← 0FF
PC ← PC + 1
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