COP87LXXCJ Datasheet, PDF (17/28 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 4k or 32k Memory and Comparator

Multi-Input Wake Up (Continued)
pop the stack into the program counter (PC). The stack
pointer is then incremented twice. The RETI instruction addi-
tionally sets the GIE bit to re-enable further interrupts.
Any of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
Note: There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit. If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit, the interrupt enable bit will be reset but
an interrupt may still occur. This is because interrupt processing is
started at the same time as the interrupt bit is being reset. To avoid this
scenario, the user should always use a two, three, or four cycle instruc-
tion to reset interrupt enable bits.
DETECTION OF ILLEGAL CONDITIONS
The device incorporates a hardware mechanism that allows
it to detect illegal conditions which may occur from coding er-
rors, noise, and “brown out” voltage drop situations. Specifi-
cally, it detects cases of executing out of undefined ROM
area and unbalanced tack situations.
Reading an undefined ROM location returns 00 (hexadeci-
mal) as its contents. The opcode for a software interrupt is
also “00”. Thus a program accessing undefined ROM will
cause a software interrupt.
Reading an undefined RAM location returns an FF (hexa-
decimal). The subroutine stack on the device grows down for
each subroutine call. By initializing the stack pointer to the
top of RAM, the first unbalanced return instruction will cause
the stack pointer to address undefined RAM. As a result the
program will attempt to execute from FFFF (hexadecimal),
which is an undefined ROM location and will trigger a soft-
ware interrupt.
FIGURE 16. Interrupt Block Diagram
DS012529-20
Control Registers
CNTRL1 REGISTER (ADDRESS 00EE)
TC3 TC2 TC1 TRUN MSEL IEDG SL1 SL0
Bit 7
Bit 0
The Timer and MICROWIRE control register contains the fol-
lowing bits:
TC3
Timer T1 Mode Control Bit
TC2
Timer T1 Mode Control Bit
TC1
Timer T1 Mode Control Bit
TRUN
Used to start and stop the timer/counter
(1 = run, 0 = stop)
MSEL
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively
IEDG
External interrupt edge polarity select
SL1 and SL0 Select the MICROWIRE clock divide-by
(00 = 2, 01 = 4, 1x = 8)
PSW REGISTER (ADDRESS 00EF)
HC C TPND ENTI IPND BUSY ENI
Bit 7
The PSW register contains the following select bits:
HC Half-Carry Flip/Flop
C
Carry Flip/Flop
TPND Timer T1 interrupt pending
(timer Underflow or capture edge)
ENTI Timer T1 interrupt enable
GIE
Bit 0
IPND External interrupt pending
BUSY MICROWIRE busy shifting flag
ENI External interrupt enable
GIE Global interrupt enable (enables interrupts)
The Half-Carry bit is also effected by all the instructions that
effect the Carry flag. The flag values depend upon the in-
struction. For example, after executing the ADC instruction
the values of the Carry and the Half-Carry flag depend upon
the operands involved. However, instructions like SET C and
RESET C will set and clear both the carry flags. Table *NO
TARGET FOR table NS2079* lists the instructions that effect
the HC and the C flags.
TABLE 9. Instructions Effecting HC and C Flags
Instr.
ADC
SUBC
SET C
RESET C
RRC
HC Flag
Depends on
Operands
Depends on
Operands
Set
Set
Depends on
Operands
C Flag
Depends on
Operands
Depends on
Operands
Set
Set
Depends on
Operands
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