COP87LXXCJ Datasheet, PDF (16/28 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 4k or 32k Memory and Comparator

Multi-Input Wake Up (Continued)
This selection is made via the Reg:WKEDG, which is an 8-bit
control register with a bit assigned to each L Port pin. Setting
the control bit will select the trigger condition to be a negative
edge on that particular L Port pin. Resetting the bit selects
the trigger condition to be a positive edge. Changing an edge
select entails several steps in order to avoid a pseudo
Wakeup condition as a result of the edge change. First, the
associated WKEN bit should be reset, followed by the edge
select change in WKEDG. Next, the associated WKPND bit
should be cleared, followed by the associated WKEN bit be-
ing re-enabled.
An example may serve to clarify this procedure. Suppose we
wish to change the edge select from positive (low going high)
to negative (high going low) for L port bit 5, where bit 5 has
previously been enabled for an input. The program would be
as follows:
RBIT 5, WKEN ; Disable MIWU
SBIT 5, WKEDG ; Change edge polarity
RBIT 5, WKPND ; Reset pending flag
SBIT 5, WKEN ; Enable MIWU
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup, a safety proce-
dure should also be followed to avoid inherited pseudo
wakeup conditions. After the selected L port bits have been
changed from output to input but before the associated
WKEN bits are enabled, the associated edge select bits in
WKEDG should be set or reset for the desired edge selects,
followed by the associated WKPND bits being cleared. This
same procedure should be used following RESET, since the
L port inputs are left floating as a result of RESET.
The occurrence of the selected trigger condition for
Multi-Input Wakeup is latched into a pending register called
Reg:WKPND. The respective bits of the WKPND register will
be set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since the Reg:WKPND is a
pending register for the occurrence of selected wakeup con-
ditions, the device will not enter the HALT mode if any
Wakeup bit is both enabled and pending. Setting the G7 data
bit under this condition will not allow the device to enter the
HALT mode. Consequently, the user has the responsibility of
clearing the pending flags before attempting to enter the
HALT mode.
If a crystal oscillator is being used, the Wakeup signal will not
start the chip running immediately since crystal oscillators
have a finite start up time. The WATCHDOG timer prescaler
generates a fixed delay to ensure that the oscillator has in-
deed stabilized before allowing the device to execute in-
structions. In this case, upon detecting a valid Wakeup signal
only the oscillator circuitry and the WATCHDOG timer are
enabled. The WATCHDOG timer prescaler is loaded with a
value of FF Hex (256 counts) and is clocked from the tc in-
struction cycle clock. The tc clock is derived by dividing down
the oscillator clock by a factor of 10. A Schmitt trigger follow-
ing the CKI on chip inverter ensures that the WATCHDOG
timer is clocked only when the oscillator has a sufficiently
large amplitude to meet the Schmitt trigger specs. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the WATCHDOG timer enables the
clock signals to be routed to the rest of the chip.
DS012529-19
FIGURE 15. Multi-Input Wakeup Logic
INTERRUPTS
The device has a sophisticated interrupt structure to allow
easy interface to the real world. There are three possible in-
terrupt sources, as shown below.
A maskable interrupt on external G0 input (positive or nega-
tive edge sensitive under software control)
A maskable interrupt on timer carry or timer capture
A non-maskable software/error interrupt on opcode zero
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to se-
lect one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.
ENI and ENTI bits select external and timer interrupts re-
spectively. Thus the user can select either or both sources to
interrupt the microcontroller when GIE is enabled.
IEDG selects the external interrupt edge (0 = rising edge, 1
= falling edge). The user can get an interrupt on both rising
and falling edges by toggling the state of IEDG bit after each
interrupt.
IPND and TPND bits signal which interrupt is pending. After
an interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high in-
side the interrupt subroutine allows nested interrupts.
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other inter-
rupt sources while servicing the software interrupt.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address 00FFH and resumes execution from
that address. This process takes 7 cycles to complete. At the
end of the interrupt subroutine, any of the following three in-
structions return the processor back to the main program:
RET, RETSK or RETI. Either one of the three instructions will
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