COP87LXXCJ Datasheet, PDF (18/28 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 4k or 32k Memory and Comparator

Control Registers (Continued)
CNTRL2 REGISTER (ADDRESS 00CC)
MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF Resvd
R/W R/W R/W R/W
R/O
R/W
R/O
Bit 7
Bit 0
MC3 Modulator/Timer Control Bit
MC2 Modulator/Timer Control Bit
MC1 Modulator/Timer Control Bit
CMPEN Comparator Enable Bit
CMPRD Comparator Read Bit
CMPOE Comparator Output Enable Bit
WDUDF WATCHDOG Timer Underflow Bit (Read Only)
Resvd This bit is reserved and must be zero
WDREG REGISTER (ADDRESS 00CD)
UNUSED
WDREN
Bit 7
Bit 0
WDREN WATCHDOG Reset Enable Bit (Write Once Only)
Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
00 to 2F
(820CJ)
00 to 6F
(840CJ)
30 to 7F
(820CJ)
70 to 7F
(840CJ)
80 to BF
C0 to C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8 to DB
DC
DD to DF
Contents
On-chip RAM bytes (48 bytes)
On-chip RAM bytes (112 bytes)
Unused RAM Address Space (Reads as All
Ones)
Unused RAM Address Space (Reads as All
Ones)
Expansion Space for On-Chip EERAM
(Reads Undefined Data)
Reserved
MIWU Edge Select Register (Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
Reserved
Control2 Register (CNTRL2)
WATCHDOG Register (WDREG)
WATCHDOG Counter (WDCNT)
Modulator Reload (MODRL)
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D
Address
Contents
E0 to EF On-Chip Functions and Registers
E0 to E7 Reserved for Future Parts
E8
Reserved
E9
MICROWIRE Shift Register
EA
Timer Lower Byte
EB
Timer Upper Byte
EC
Timer1 Autoreload Register Lower Byte
ED
Timer1 Autoreload Register Upper Byte
EE
CNTRL1 Control Register
EF
PSW Register
F0 to FF On-Chip RAM Mapped as Registers
FC
X Register
FD
SP Register
FE
B Register
Reading other unused memory locations will return unde-
fined data.
Addressing Modes
There are ten addressing modes, six for operand addressing
and four for transfer of control.
OPERAND ADDRESSING MODES
REGISTER INDIRECT
This is the “normal” addressing mode for the chip. The oper-
and is the data memory addressed by the B or X pointer.
REGISTER INDIRECT WITH AUTO POST INCREMENT
OR DECREMENT
This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the B
or X pointer. This is a register indirect mode that automati-
cally post increments or post decrements the B or X pointer
after executing the instruction.
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
IMMEDIATE
The instruction contains an 8-bit immediate field as the oper-
and.
SHORT IMMEDIATE
This addressing mode issued with the LD B,# instruction,
where the immediate # is less than 16. The instruction con-
tains a 4-bit immediate field as the operand.
INDIRECT
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES
RELATIVE
This mode is used for the JP instruction with the instruction
field being added to the program counter to produce the next
instruction address. JP has a range from −31 to +32 to allow
a one byte relative jump (JP + 1 is implemented by a NOP in-
struction). There are no “blocks” or “pages” when using JP
since all 15 bits of the PC are used.
ABSOLUTE
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