COP87LXXCJ Datasheet, PDF (10/28 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 4k or 32k Memory and Comparator

MICROWIRE/PLUS (Continued)
changes (Figure 7). The MSEL bit in the CNTRL register
must be set to enable the SO and SK functions on the G
Port. The SO and SK pins must also be selected as outputs
by setting appropriate bits in the Port G configuration regis-
ter. Table 4 summarizes the bit settings required for Master
mode of operation.
Slave MICROWIRE/PLUS Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
on the G Port. The SK pin must be selected as an input and
the SO pin selected as an output pin by appropriately setting
up the Port G configuration register. Table 4 summarizes the
settings required to enter the Slave mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be re-
peated (see Figure 7).
TABLE 4.
G4
G5
G4
G5 G6
Config. Config. Fun. Fun. Fun.
Bit
Bit
1
1
SO
Int. SI
SK
0
1 TRI-STATE Int. SI
SK
1
0
SO
Ext. SI
SK
0
0 TRI-STATE Ext. SI
SK
Operation
MICROWIRE
Master
MICROWIRE
Master
MICROWIRE
Slave
MICROWIRE
Slave
FIGURE 7. MICROWIRE/PLUS Application
DS012529-8
www.national.com
10