COP87LXXCJ Datasheet, PDF (12/28 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 4k or 32k Memory and Comparator

WATCHDOG
The device has an on-board 8-bit WATCHDOG timer. The
timer contains an 8-bit READ/WRITE down counter clocked
by an 8-bit prescaler. Under software control the timer can
be dedicated for the WATCHDOG or used as a general pur-
pose counter. Figure 11 shows the WATCHDOG timer block
diagram.
FIGURE 11. WATCHDOG Timer Block Diagram
DS012529-13
MODE 1: WATCHDOG TIMER
The WATCHDOG is designed to detect user programs get-
ting stuck in infinite loops resulting in loss of program control
or “runaway” programs. The WATCHDOG can be enabled or
disabled (only once) after the device is reset as a result of
external reset. On power-up the WATCHDOG is disabled.
The WATCHDOG is enabled by writing a “1” to WDREN bit
(resides in WDREG register). Once enabled, the user pro-
gram should write periodically into the 8-bit counter before
the counter underflows. The 8-bit counter (WDCNT) is
memory mapped at address 0CE Hex. The counter is loaded
with n-1 to get n counts. The counter underflow resets the
device, but does not disable the WATCHDOG. Loading the
8-bit counter initializes the prescaler with FF Hex and starts
the prescaler/counter. Prescaler and counter are stopped
upon counter underflow. Prescaler and counter are each
loaded with FF Hex when the device goes into the HALT
mode. The prescaler is used for crystal/resonator start-up
when the device exits the HALT mode through Multi-Input
Wakeup. In this case, the prescaler/counter contents are
changed.
MODE 2: TIMER
In this mode, the prescaler/counter is used as a timer by
keeping the WDREN (WATCHDOG reset enable) bit at 0.
The counter underflow sets the WDUDF (underflow) bit and
the underflow does not reset the device. Loading the 8-bit
counter (load n-1 for n counts) sets the WDTEN bit (WATCH-
DOG Timer Enable) to “1”, loads the prescaler with FF, and
starts the timer. The counter underflow stops the timer. The
WDTEN bit serves as a start bit for the WATCHDOG timer.
This bit is set when the 8-bit counter is loaded by the user
program. The load could be as a result of WATCHDOG ser-
vice (WATCHDOG timer dedicated for WATCHDOG func-
tion) or write to the counter (WATCHDOG timer used as a
general purpose counter). The bit is cleared upon Brown Out
reset, WATCHDOG reset or external reset. The bit is not
memory mapped and is transparent to the user program.
CONTROL/STATUS BITS
WDUDF: WATCHDOG Timer Underflow Bit
This bit resides in the CNTRL2 Register. The bit is set when
the WATCHDOG timer underflows. The underflow resets the
device if the WATCHDOG reset enable bit is set (WDREN =
1). Otherwise, WDUDF can be used as the timer underflow
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